MOS Transistor Active-Area Recessing to Limit NMOS Dislocations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NMOS transistors in electronic circuits are prone to dislocations, which affect their functionality and increase off-state current, particularly when manufactured alongside PMOS transistors on the same manufacturing line, leading to performance degradation.
Innovation Solution
The manufacturing method involves forming NMOS and PMOS transistors with insulating regions of varying depths, where the NMOS transistor's active area is recessed by a greater depth to reduce dislocation risk without degrading PMOS transistor performance, and optional counter-doping is applied to mitigate the hump effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If arsenic is used as a dopant in NMOS transistors, then doping effectiveness is improved, but dislocation occurrence increases
Solution Approach 1:
The patent changes the dopant type parameter from arsenic to phosphorus in NMOS transistors manufactured on the same line as PMOS transistors. This parameter change reduces dislocation occurrence while maintaining acceptable doping effectiveness, resolving the contradiction between manufacturing precision and reliability.
2Manufacturing precision
If implantation dose is increased to improve doping, then doping effectiveness is improved, but dislocation risk increases
Solution Approach 1:
The patent changes the dopant type parameter from arsenic to phosphorus, which allows for effective doping at lower implantation doses. This parameter change reduces the risk of dislocations while maintaining doping effectiveness, resolving the contradiction between manufacturing precision and reliability.
Data Source
AI summary
An electronic circuit includes a plurality of transistors including: at least one first MOS transistor of a first conductivity type arranged inside and on top of at least one first active area of a semiconductor substrate and at least one second MOS transistor of the second conductivity type arranged inside and on top of at least one second active area of the semiconductor substrate. Each first active area is delimited by a first insulating region which is recessed with respect to a first surface of the semiconductor substrate by a first depth. Each second active area is delimited by a second insulating region which is flush with the first surface of the semiconductor substrate, or which is recessed with respect to the first surface of the semiconductor substrate by a second depth smaller than the first depth.