MOS Structures with Remote Contacts for Reduced Resistance
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Solution Overview
Problem
Conventional MOS transistor contact manufacturing techniques face challenges such as increased resistance due to shrinking device sizes, misalignment issues leading to thinner dielectric layers and current leakage, and compromise of stress layers, which affect device performance.
Innovation Solution
The method involves forming conductive contacts remote from gate electrodes, using a semiconductor layer surrounded by an isolation region with parallel gate stacks and a highly intrinsically-stressed layer, allowing the contact to be fabricated outside the space between gate electrodes, thereby reducing resistance and minimizing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the contact size is decreased to accommodate more circuitry, then the device integration density is improved, but the contact resistance increases
Solution Approach 1:
The contact is moved from the traditional position between gate electrodes to a remote location at the end of the gate electrode. This spatial repositioning in a different dimension allows the contact to maintain a larger effective area for lower resistance while still serving the scaled-down device, thus resolving the contradiction between integration density and contact resistance.
2Reliability
If the contact is made larger to reduce resistance, then the contact resistance is improved, but the dielectric thickness between contact and gate electrode decreases
Solution Approach 1:
The contact is extracted from its traditional position between the gate electrodes and relocated to a remote position at the gate end. This separation removes the conflict between contact size and dielectric thickness, allowing the contact to be sufficiently large for low resistance without encroaching on the gate electrode spacing and compromising dielectric integrity.
3Ease of manufacture
If the contact opening is etched at an angle or misaligned, then the manufacturing process becomes easier, but the dielectric layer between contact and gate electrode becomes thinner
Solution Approach 1:
By relocating the contact opening to a remote position away from the gate electrodes, the etching process gains more tolerance for angular deviations and misalignments. The increased spatial buffer means that even if the etch angle varies or mask overlay shifts occur, the contact will not encroach on the gate electrode region, thus maintaining adequate dielectric thickness despite manufacturing variations.
4Ease of manufacture
If the contact is formed through the stress layer, then the contact fabrication is simplified, but the stress layer effectiveness is compromised
Solution Approach 1:
The contact is extracted from the traditional path through the stress layer and relocated to a remote position. This allows the stress layer to remain intact and continuous over the active device regions, preserving its stress-induced mobility enhancement effects. The contact can still be formed through simplified processes but at a location where it does not interfere with the stress layer's beneficial effects on device performance.
Data Source
AI summary
MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.