MOS Power-On Reset Circuit for Slow Supply Rise Stability
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Solution Overview
Problem
Conventional power-on reset circuits face challenges in stabilizing the output of reset signals during slow power supply rises and momentary power outages, and they require large resistance values and complex structures to reduce power consumption, making them bulky and difficult to control.
Innovation Solution
A power-on reset circuit design utilizing a first-conductive-type MOS transistor and a second-conductive-type MOS transistor with a bias potential independent of the power supplies, along with sensor circuits and a reset signal generating circuit to ensure stable reset signal output without the need for high resistance resistors, thereby reducing circuit size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a resistor of extremely large resistance value is used to reduce power consumption, then power consumption is reduced, but the resistor occupies a large area on the semiconductor integrated circuit
Solution Approach 1:
The invention changes the operating parameters of MOS transistors (threshold voltage, channel width, channel length) to replace the function of high-value resistors. By carefully selecting transistor dimensions and threshold voltages, the circuit achieves the same current limiting function without requiring large-area resistors, thus reducing overall circuit area while maintaining low power consumption.
Solution Approach 2:
The invention substitutes passive resistor-based current limiting with active MOS transistor-based current control. The MOS transistors function as voltage-controlled current sources, replacing the need for physical resistors and enabling more compact circuit design with equivalent or superior power efficiency.
2Adaptability or versatility
If the bias circuit output potential depends on the power supply potential, then the circuit can operate with power supply variations, but the bias circuit cannot be independently used and current control becomes difficult
Solution Approach 1:
The invention separates the bias generation function from the power supply voltage, creating an independent bias circuit that can be controlled separately. The bias circuit uses reference voltages and controlled current sources that are not directly tied to power supply variations, enabling independent current control while maintaining adaptability to different power supply conditions.
Solution Approach 2:
The invention introduces intermediate reference voltage circuits and controlled current mirrors as mediators between the power supply and the bias circuit. These intermediaries decouple the bias circuit from direct power supply dependence, allowing independent current control while still providing adaptability to power supply variations through regulated reference voltages.
3Reliability
If the potential V1 rises more slowly than VDD through integration circuit, then the reset signal can be generated, but V1 cannot reach the threshold voltage VT when power rises slowly
Solution Approach 1:
The invention uses dynamic current control through MOS transistors that automatically adjust their conductance based on instantaneous voltage conditions. The transistor operating points shift dynamically with power supply voltage, providing faster response to voltage changes compared to static RC integration circuits, while still ensuring reliable reset signal generation through controlled current paths.
Solution Approach 2:
The invention changes the circuit parameters from fixed RC time constants to dynamically controllable MOS transistor characteristics. By adjusting transistor threshold voltages, channel widths, and lengths, the circuit achieves both fast response to power supply changes and reliable reset signal generation, overcoming the speed limitation of traditional integration circuits.
4Reliability
If conventional power-on reset circuit structure is used, then the circuit can operate, but the circuit size is large and current control is difficult
Solution Approach 1:
The invention merges multiple functions (current limiting, voltage regulation, reset signal generation, and bias control) into a single integrated MOS transistor circuit. By combining these functions that were previously implemented by separate components (resistors, bias circuits, voltage regulators), the design achieves compact size and simplified structure while maintaining reliable reset operation.
Solution Approach 2:
The invention creates a universal MOS transistor-based circuit block that performs multiple functions simultaneously: current limiting, voltage reference generation, reset signal production, and adaptive bias control. This multi-functional approach eliminates the need for separate dedicated circuits for each function, reducing overall device complexity and improving integration efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables stable reset signal output even during slow power supply rises and momentary power outages, reducing the circuit size and power consumption by eliminating the need for high resistance components, allowing for independent current control and efficient operation.
Implementation Method 1
a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate
Data Source
AI summary
A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.