MOS Device Schottky Barrier Layer On-Resistance Reduction
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Solution Overview
Problem
Power MOS devices face limitations in reducing on-resistance and gate capacitance, which affect the efficiency and reliability of power switches in applications like DC-DC converters, due to manufacturing constraints and the punch-through phenomenon.
Innovation Solution
The development of a DMOS device fabrication process that includes shallower source and body regions, increased cell density, and the use of anti-punch through implants and Schottky diodes to reduce on-resistance and gate capacitance, while maintaining good breakdown characteristics and reducing switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is reduced by using shallower source and body regions, then the on-resistance is reduced, but the punch-through phenomenon occurs
Solution Approach 1:
The patent applies local quality by creating different doping concentrations in specific regions. The first dopant concentration in the body region is lower than the second dopant concentration in the source region, creating a graded structure that reduces on-resistance while preventing punch-through through localized doping variations.
Solution Approach 2:
The patent changes the doping concentration parameter by implanting two different dopants with different concentrations. The body region receives a first dopant at a first concentration while the source region receives a second dopant at a higher concentration, fundamentally changing the electrical parameters to resolve the contradiction between low on-resistance and punch-through prevention.
2Loss of energy
If the number of cells per unit area is increased by reducing cell size, then the on-resistance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the device into discrete cells with gates, sources, and bodies. By increasing the number of these segmented cells per unit area through reduced cell size, the patent achieves lower on-resistance while the segmented structure allows for systematic manufacturing approaches.
Solution Approach 2:
The patent changes the cell density parameter by reducing cell size to increase the number of cells per unit area. This parameter change directly reduces on-resistance while the invention provides a fabrication process that manages the manufacturing complexity through controlled ion implantation and thermal processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces on-resistance and gate capacitance, enhancing the reliability and power consumption of power switches, improving efficiency in applications such as synchronous rectification and DC-DC converters.
Implementation Method 1
forming a Schottky barrier controlling layer of a second dopant type and a second dopant concentration in a region underneath the contact electrode
Data Source
AI summary
A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body into the drain region; an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain region form a Schottky diode; and a Schottky barrier controlling layer.