MOS-SCR ESD Protection Device with Doped Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electrostatic discharge (ESD) protection devices for integrated circuits (ICs) face challenges in achieving low on-resistance, low trigger voltage, and high withstanding voltage, making them vulnerable to ESD events that can lead to destruction or explosion of ICs.
Innovation Solution
The ESD protection device incorporates doped regions in a metal oxide semiconductor (MOS) structure to form silicon control rectifier (SCR) configurations, which enhance the ESD protection performance by providing bi-directional protection and reducing on-resistance while increasing the second breakdown current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection structures are used, then the device can provide basic ESD protection, but the on-resistance is high and the trigger voltage is not low enough
Solution Approach 1:
The patent combines MOS and SCR structures into a unified ESD protection device. The MOS structure provides low on-resistance during normal operation, while the SCR structure provides low trigger voltage and high breakdown current during ESD events. This merging allows the device to simultaneously achieve low on-resistance and low trigger voltage, resolving the technical contradiction between basic protection capability and optimal ESD performance parameters.
Solution Approach 2:
The patent employs a composite structure integrating two different semiconductor device types (MOS and SCR) with complementary characteristics. The MOS portion contributes low resistance channels, while the SCR portion provides snap-back behavior with low trigger voltage. This composite approach enables the device to overcome the limitations of individual structures and achieve superior ESD protection performance.
2Reliability
If conventional ESD protection structures are used, then the device can operate normally, but the withstanding voltage is insufficient and the second breakdown current is low
Solution Approach 1:
The integrated MOS-SCR structure enables the device to achieve high withstanding voltage through the SCR's snap-back characteristic while simultaneously providing high second breakdown current. The MOS structure maintains proper voltage levels during normal operation, and the SCR structure activates during ESD events to provide the necessary current handling capability, thus resolving the contradiction between withstanding voltage and breakdown current.
3Ease of manufacture
If simple ESD protection structures are used, then the manufacturing process is simple, but the ESD protection performance is insufficient
Solution Approach 1:
The patent integrates MOS and SCR structures into a single device that can be manufactured using standard semiconductor fabrication processes. The shared substrate and integrated architecture allow both structures to be formed in sequence using conventional doping, oxidation, and deposition techniques, achieving complex ESD protection functionality without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves the ESD protection performance by reducing on-resistance and enhancing the second breakdown current, providing robust bi-directional protection against ESD events, thus safeguarding ICs from damage.
Implementation Method 1
electrostatic discharge (ESD) is a constant threat to modern electronics. The result of ESD on unprotected ICs is often destruction
Implementation Method 2
the ESD surges will cause the ESD protection device breakdown and create a substrate current path, through which the ESD current is diverted to ground
Data Source
AI summary
An ESD protection device includes a semiconductor substrate, a well, a gate structure, a first source/drain region, a second source/drain region, a first doped region, and a second doped region. The well is disposed in the semiconductor substrate. The gate structure is disposed on the well. The first source/drain region and the second source/drain region are disposed in the well and disposed at two opposite sides of the gate structure respectively. The first doped region is disposed in the first source/drain region. The second doped region is disposed in the second source/drain region. A conductivity type of the first doped region is complementary to that of the first source/drain region. A conductivity type of the second doped region is complementary to that of the second source/drain region. A conductivity type of the well is complementary to that of the first source/drain region and the second source/drain region.