MOS Device Low Resistance Silicide Interface
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Solution Overview
Problem
Current CMOS device manufacturing faces challenges in achieving low silicide interface resistance while minimizing yield-reducing defects like pipes and short channel effects, which limits transistor speed and yield.
Innovation Solution
A method involving ultra-shallow second dopant implants followed by a low-temperature silicide anneal to achieve high dopant concentrations at the silicide interface, reducing interface resistance and pipe density while maintaining acceptable short channel behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-amorphization implant is performed before silicidation to prevent pipe formation, then pipe density is reduced, but active dopant concentration at the surface is deactivated
Solution Approach 1:
The implantation process is divided into two separate steps: first a pre-amorphization implant to create amorphous silicon and prevent pipe formation, then a second dopant implant to restore and enhance the dopant concentration at the surface. This segmentation allows each implant to serve its specific function without interfering with the other.
Solution Approach 2:
The pre-amorphization implant is performed as a preliminary action before the main dopant implantation. This preliminary step prepares the silicon lattice by creating amorphous regions that will prevent pipe formation during subsequent processing, while the second implant then adds the necessary dopant concentration.
2Quantity of substance
If higher reaction temperature silicide is used to increase active dopant concentration, then silicide interface resistance decreases, but silicide agglomeration occurs reducing yield
Solution Approach 1:
The implantation energy and dose parameters are optimized to achieve the desired dopant concentration profile. By carefully controlling the implantation parameters, high dopant concentration is achieved at the surface without requiring excessive temperature that would cause agglomeration.
3Speed
If higher doping concentration is used to reduce silicide interface resistance, then transistor speed increases, but short channel effect increases
Solution Approach 1:
The dopant concentration is made non-uniform through the two-step implantation process, with higher concentration at the surface (for low contact resistance) and controlled concentration deeper in the substrate (to maintain short channel behavior). This local variation in dopant quality allows simultaneous optimization of both contact resistance and transistor performance.
Solution Approach 2:
The dopant concentration is optimized in the vertical dimension (depth profile) through controlled implantation. By managing the depth distribution of dopants, the surface concentration is maximized for low resistance while the deeper concentration is controlled to prevent short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces silicide interface resistance and pipe density, enhancing transistor performance and yield by achieving high dopant concentrations at the silicide interface without degrading short channel behavior.
Implementation Method 1
a first S/D implant of a first dopant type is implanted, and a second S/D implant of the first dopant type is implanted into a surface portion of the source and drain
Implementation Method 2
The first and second S/D implants are annealed. A silicide anneal is performed
Data Source
AI summary
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.