MOS Transistor Spacer Structure for High-Voltage Field Control
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Solution Overview
Problem
Existing MOS transistor manufacturing methods result in spacers with varying widths, which can become a problem for transistors that need to withstand high voltages, as the width of the spacers decreases with the height of the transistors.
Innovation Solution
The method involves forming parallelepiped-shaped spacers before the gate is created, using a process that includes depositing an insulator layer and etching it to form the spacers, which maintains a constant width along the entire height of the spacers, independent of the gate height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spacers are formed after the gate using conventional methods, then the manufacturing process follows standard sequence, but the spacer width varies with gate height which reduces reliability for high-voltage applications
Solution Approach 1:
The spacers are formed before the gate is created, reversing the conventional sequence. This preliminary formation of spacers ensures their width is determined by the insulation layer thickness rather than gate height, providing consistent spacer dimensions independent of subsequent gate formation variations.
Solution Approach 2:
The conventional gate-first manufacturing sequence is inverted to spacer-first. This inversion fundamentally changes how spacer dimensions are controlled, making them independent of gate height and ensuring uniform width that maintains reliability under high voltage conditions.
2Power
If transistor height is increased to withstand higher voltages, then voltage withstanding capability improves, but spacer width decreases which reduces input resistance
Solution Approach 1:
By forming spacers before the gate, their width is established by the insulation layer thickness before any gate structure is created. This preliminary action decouples spacer width from gate height, allowing transistors to be scaled for higher voltages without compromising spacer dimensions and input resistance.
Solution Approach 2:
The method changes the controlling parameter for spacer width from gate height to insulation layer thickness. This parameter change enables independent optimization of transistor voltage withstanding capability (through gate height) and input resistance (through spacer width controlled by insulation layer).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the spacers maintain a consistent width, which helps in adjusting the electric field and improving the input resistance of the transistors, particularly for high-voltage applications.
Implementation Method 1
depositing a layer of insulator
Implementation Method 2
depositing a layer of insulator
Implementation Method 3
etching the insulator layer to form the spacers
Implementation Method 4
etching the insulator layer to form the spacers
Implementation Method 5
oxidizing a layer of semiconductor material of a substrate of silicon-on-insulator type
Data Source
AI summary
A MOS transistor including a substrate, a conductive having lateral walls, drain and source regions, and spacers having an upper surface such that the spacers are buried in the substrate and are position between the conductive gate and the drain and source regions is provided. The spacers are each cuboid-shaped and have a width that is constant along the spacers height and independent from a height of the conductive gate. A device including the MOS transistor and a method of manufacture for producing a right-hand portion and a left-hand portion of a MOS transistor is also provided.