Multi-Voltage MOS Transistor Spacer Structure for GIDL Control
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Solution Overview
Problem
Existing integrated structures of MOS transistors with different working voltages face issues with gate-induced drain leakage (GIDL) in medium voltage (MV) devices, particularly exceeding the desired threshold of 10 pA/μm, and require improvements in integration and device density.
Innovation Solution
The method involves forming MOS transistors with varying working voltages by stacking gate dielectric and conductive material layers, using multiple sub-spacers to adjust spacer thicknesses, and optimizing source/drain regions through self-aligned processes to reduce GIDL and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the second gate dielectric layer is increased to reduce GIDL leakage in MV devices, then the GIDL leakage is reduced, but the device area and integration density are adversely affected
Solution Approach 1:
The gate dielectric layer is segmented into three distinct layers with different thicknesses: first gate dielectric layer (thin), second gate dielectric layer (thick for GIDL reduction), and third gate dielectric layer (medium). This segmentation allows each layer to serve specific functions - the thick second layer reduces GIDL leakage in MV devices while the overall structure maintains compact dimensions for integration.
Solution Approach 2:
Different regions of the gate dielectric structure have different thicknesses tailored to specific functional requirements. The second gate dielectric layer is locally thickened in regions where GIDL reduction is critical, while other regions maintain thinner profiles to preserve device density and integration.
2Reliability
If multiple sub-spacers are used to adjust spacer thickness for optimizing MV device performance, then GIDL leakage is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The spacer structure is segmented into multiple sub-spacers (first sub-spacer, second sub-spacer, third sub-spacer) with different thicknesses. Each sub-spacer is formed through separate deposition and etching steps, allowing independent thickness control to optimize device performance while managing process complexity through systematic fabrication sequences.
Solution Approach 2:
The thickness parameters of different sub-spacers are independently adjusted to achieve optimal device performance. By changing the thickness of specific sub-spacers (particularly the second and third sub-spacers), the patent optimizes GIDL leakage characteristics without requiring complete redesign of the entire spacer system.
3Productivity
If the thickness of the first gate dielectric layer is reduced to improve integration density, then device integration is improved, but the voltage withstanding capability may be compromised
Solution Approach 1:
The gate dielectric is segmented into three layers where the first layer is thin (for integration density), the second layer is thick (for voltage withstanding and GIDL reduction), and the third layer provides additional functionality. This segmentation allows the thin first layer to improve integration while the thick second layer compensates for voltage withstanding requirements.
Solution Approach 2:
The gate dielectric structure uses a composite of three different dielectric layers, each with optimized thickness and material properties. This composite structure achieves a balance between integration density (thin first layer) and voltage withstanding capability (thick second layer), demonstrating the effectiveness of composite material design in resolving conflicting requirements.
Data Source
AI summary
The present application discloses an integrated structure of MOS transistors having different working voltages. A second spacer of a second MOS transistor having a middle second working voltage is formed by adding a third sub-spacer on the basis of a first spacer of a first MOS transistor having a relatively low first working voltage, and the first spacer is formed by stacking a first sub-spacer and a second sub-spacer. The thickness of the second spacer is adjusted via the third sub-spacer, so as to ensure that a GIDL leakage of the second MOS transistor under the second working voltage satisfies a requirement. The present application also discloses a method for manufacturing an integrated structure of MOS transistors having different working voltages.