MOS Transistor Spacer Void Formation to Protect Epitaxial Layers
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Solution Overview
Problem
Current methods for forming MOS transistors with epitaxial layers often damage the surface of the epitaxial layer, affecting device performance due to the sequence of removing interlayer dielectric layers and depositing metals.
Innovation Solution
A method involving forming a gate structure, spacers, and a recess, followed by a cleaning process to create a void between the spacers and the substrate, and finally growing an epitaxial layer in the recess.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interlayer dielectric layer is removed and metals are deposited after forming the epitaxial layer, then the contact hole can be formed and electrical connection achieved, but the surface of the epitaxial layer is damaged and device performance is affected
Solution Approach 1:
The patent performs the cleaning process and forms the void between the spacer and substrate before depositing the epitaxial layer. This preliminary action prevents subsequent processing steps from damaging the epitaxial layer surface, as the void creates a protective gap that isolates the layer from mechanical contact during metal deposition and contact hole formation.
Solution Approach 2:
The void formed by the cleaning process acts as an intermediary protective structure between the spacer/substrate and the epitaxial layer. This intermediate space prevents direct contact and potential damage during subsequent processing, allowing the epitaxial layer to maintain its surface integrity while still enabling electrical connection functionality.
2Reliability
If the cleaning process is performed to form a void between spacer and substrate, then surface damage to epitaxial layer is prevented, but the fabrication process complexity increases
Solution Approach 1:
The patent combines the cleaning process with the spacer formation steps, performing the cleaning to form the void during the same fabrication sequence where spacers are already being created. This merging of operations adds minimal process complexity while achieving the protective void formation, as the cleaning step is integrated into the existing spacer fabrication flow rather than being a separate additional operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the fabrication process by reducing spacer thickness and forming a void, which helps in preventing surface damage to the epitaxial layer, thereby enhancing device performance and reliability.
Implementation Method 1
performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate
Implementation Method 2
forming an epitaxial layer in the recess
Data Source
AI summary
A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.