Stress Memorization via Ion Implantation in MOS Transistors
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Solution Overview
Problem
Current semiconductor device fabrication techniques fail to effectively increase carrier mobility in MOS devices by optimizing stress levels in the channel region, which is crucial for improved performance and integration density.
Innovation Solution
A method involving the formation of a tensile stress layer over MOS transistors, followed by ion implantation and annealing to enhance and memorize stress, increasing the stress level in the channel region and thereby enhancing electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If ion implantation and annealing are performed on the stress layer, then the tensile stress in the channel region is significantly increased, but the process complexity and manufacturing steps increase
Solution Approach 1:
The patent applies parameter changes by modifying the stress layer through ion implantation (changing material composition) and thermal annealing (changing temperature parameters). This transforms the stress layer's physical and chemical properties to generate enhanced tensile stress in the channel region, directly resolving the contradiction between achieving high stress and maintaining process simplicity.
2Reliability
If the stress layer is formed over the MOS transistor, then electron mobility is enhanced, but the device structure becomes more complex
Solution Approach 1:
The patent applies local quality by forming a stress layer specifically over the MOS transistor channel region where stress is needed to enhance carrier mobility. The stress layer is selectively positioned and configured to provide localized stress enhancement only where required, rather than uniformly across the entire device, thus improving mobility while minimizing structural complexity.
3Speed
If integration density is increased by reducing element size, then signal propagation time is reduced, but the ability to optimize stress levels in the channel region deteriorates
Solution Approach 1:
The patent applies parameter changes by using ion implantation energy and dose parameters, along with annealing temperature and time parameters, to precisely control and optimize the stress level in the channel region. This allows for fine-tuning of stress characteristics even in miniaturized devices, maintaining manufacturing precision for stress optimization despite reduced element sizes and increased integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly increases the tensile stress in the channel region, leading to improved device performance and increased integration density without excessive cost or material usage.
Implementation Method 1
mechanical stress in the channel region of an FET can increase or decrease carrier mobility significantly; depending on the sign of the stress (e.g. tensile or compressive) and the carrier type (e.g. electron or hole). Tensile stress increases electron mobility
Implementation Method 2
implanting ions into the stress layer
Implementation Method 3
performing an anneal of the substrate and stress layer whereby the implant and anneal increase the stress on the channel region of the MOS transistor
Data Source
AI summary
Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.