MOS Transistor Stress Transfer with Removable Sidewall Spacers
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Solution Overview
Problem
Existing methods for applying physical stress to the channel region of MOS transistors to increase carrier mobility are ineffective when the distance between adjacent gate electrodes is narrow, resulting in insufficient stress and mobility enhancement.
Innovation Solution
A semiconductor device manufacturing process that involves forming a tensile/compressive film as a contact etch stop liner (CESL) and selectively removing side wall films to widen the gate electrode interval, allowing sufficient stress to be applied to the channel region, even in densely packed MOS transistors, and optionally forming an epitaxial layer in recessed regions to further enhance stress application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS transistors are densely packed to increase device integration, then device density and productivity are improved, but the gate electrode interval becomes narrow which prevents sufficient stress application to the channel region
Solution Approach 1:
The patent divides the gate electrode structure into multiple segments by introducing dummy gate electrodes between adjacent functional gate electrodes. This segmentation increases the effective gate electrode interval, allowing sufficient stress application to the channel region while maintaining high device density through compact arrangement of the segmented gates
Solution Approach 2:
The patent embeds dummy gate electrodes within the gate electrode structure of adjacent MOS transistors. These nested dummy gates occupy space within the overall gate structure without significantly increasing the external footprint, thereby increasing the effective gate interval for stress application while maintaining high device integration density
2Reliability
If the gate electrode interval is widened to apply sufficient stress to the channel region, then carrier mobility and switching rate are improved, but device density and integration are reduced
Solution Approach 1:
The patent applies stress enhancement locally by introducing dummy gate electrodes only in specific regions where stress application is critical, rather than uniformly increasing gate intervals across all transistors. This allows sufficient stress application to the channel region while maintaining high device density in other areas through compact gate spacing
Solution Approach 2:
The patent utilizes the vertical dimension by embedding dummy gate electrodes within the gate structure's depth, rather than only expanding in the horizontal plane. This three-dimensional arrangement increases the effective gate interval for stress application while maintaining compact two-dimensional device footprint for high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively increases carrier mobility and reduces leakage current in densely packed MOS transistors by ensuring sufficient physical stress is applied to the channel region, even at high transistor densities, thereby improving switching speed and performance.
Implementation Method 1
A method of applying physical stress to a channel region to increase the carrier mobility is known as a method for increasing the switching rate of a MOS transistor
Implementation Method 2
Examples of the method of applying physical stress to a channel region include a method of covering a MOS transistor with a contact etch stop liner (CESL) and a method of embedding an epitaxial layer in source/drain regions
Data Source
AI summary
An example method includes forming a gate electrode on an active region of a semiconductor substrate surrounded by a STI region; implanting a first dopant into the active region by using the gate electrode as a mask to form LDD regions; forming a liner film on top and side surfaces of the gate electrode, the STI region, and the LDD regions; forming a side wall spacer on the side surfaces of the gate electrode with the liner film interposed therebetween; implanting, with covering the STI region and the LDD regions by the liner film, a second dopant by using the gate electrode, the liner film formed on the side surfaces of the gate electrode, and the side wall spacer as a mask to form source/drain regions; and removing the side wall spacer.