MOS Source/Drain Surface Doping for Lower Contact Resistance
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Solution Overview
Problem
Reducing contact resistance of source/drain regions in MOS devices, particularly at 16/14 nm technical nodes and below, is a critical challenge for improving device performance.
Innovation Solution
Increasing the concentration of activated dopants at the surface of the source and drain by amorphizing and oxidizing the doped regions, followed by forming a metal silicide, which enhances dopant segregation and reduces contact resistance without increasing junction depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping methods are used to increase dopant concentration at source/drain surfaces, then contact resistance reduction is limited, but junction depth increases which degrades device performance
Solution Approach 1:
The patent changes the physical state of the semiconductor surface from crystalline to amorphous through ion implantation, creating a distinct phase boundary that enables dopant segregation during subsequent oxidation. This parameter change (crystalline→amorphous) allows dopants to concentrate at the surface without increasing junction depth, as the amorphous layer acts as a barrier that confines dopants during the oxidation process
Solution Approach 2:
The patent utilizes phase transition of the semiconductor surface material from crystalline to amorphous state through low-energy ion implantation. This phase transition creates a unique interface where dopants segregate during oxidation, enabling surface concentration enhancement while maintaining controlled junction depth. The phase transition is the key mechanism that decouples surface doping from junction depth control
2Quantity of substance
If ion implantation energy is increased to enhance dopant activation, then dopant concentration at surface increases, but damage to the crystal structure increases
Solution Approach 1:
The patent changes the energy parameter of ion implantation to a low range (0.5-3 keV), which is sufficient to amorphize the surface layer but not high enough to cause extensive crystal damage. This parameter optimization enables dopant incorporation while maintaining the ability to recover crystal structure through subsequent thermal treatment, achieving high dopant concentration without permanent structural degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces contact resistance by increasing dopant concentration at the surface, improving carrier tunneling probability and maintaining compatibility with CMOS techniques.
Implementation Method 1
amorphizing the doped source-or-drain portion to form an amorphous layer on a surface of the source-or-drain portion
Implementation Method 2
oxidizing the source-or-drain portion to segregate dopants in adjacency of the amorphous layer
Implementation Method 3
oxidizing the source-or-drain portion to segregate dopants in adjacency of the amorphous layer; concentration of activated dopants is increased at surfaces of a source and a drain
Data Source
AI summary
A method for manufacturing a MOS device, comprising: providing a substrate comprising a gate portion and a source-or-drain portion, where a through hole is formed in a dielectric layer disposed on the substrate and exposes a surface of the source-or-drain portion; doping the source-or-drain portion; amorphizing the doped source-or-drain portion to form an amorphous layer on a surface of the source-or-drain portion; oxidizing the source-or-drain portion to segregate dopants in adjacency of the amorphous layer; removing the oxidized amorphous layer; and forming a metal silicide on the surface of the source-or-drain portion. Contact resistance of a source and/or a drain is significantly reduced.