MOS Switch Slew-Rate Control for Clock Feedthrough Cancellation

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Solution Overview

Problem

MOS switches in semiconductor integrated circuits experience voltage errors due to charge movement caused by clock feedthrough, which affects the accuracy of analog-to-digital conversion in high-resolution SAR-ADCs.

Innovation Solution

The implementation of a MOS switch configuration with a first main MOS transistor, a dummy MOS transistor, and a switch control circuit that adjusts the slew rate of gate voltages supplied to both transistors, optimizing the slew rate to minimize charge movement and reduce voltage errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a MOS switch is used in a SAR-ADC circuit, then the switching function is achieved, but clock feedthrough causes charge movement and voltage errors that degrade conversion accuracy

Engineering Contradiction:

Improveconversion accuracyVSAvoidclock feedthrough effect

Core Design Contradiction:

Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

A dummy MOS transistor is introduced as an intermediary element connected in parallel with the main MOS transistor. The dummy transistor acts as a mediator that generates compensating charge to counterbalance the charge movement caused by clock feedthrough in the main transistor, thereby reducing voltage errors and improving conversion accuracy

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The switch control circuit generates complementary control signals for both the main and dummy MOS transistors based on the clock signal. This feedback mechanism ensures that the dummy transistor switches in opposition to the main transistor, creating a compensating effect that cancels out the harmful charge movement from clock feedthrough

Inventive Principle:

Principle #23Feedback

2Productivity

If the switching speed is increased to improve productivity, then the SAR-ADC operation is faster, but the slew rate of gate voltages increases which exacerbates clock feedthrough effects

Engineering Contradiction:

Improveswitching speedVSAvoidclock feedthrough effect

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The invention converts the harmful clock feedthrough effect into a beneficial compensating mechanism. By intentionally introducing a dummy transistor that experiences similar clock feedthrough, the harmful charge movement in the main transistor is counterbalanced, transforming the problem into a solution where the same physical effect works in favor of reducing voltage errors

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The switch control circuit adjusts the slew rate of gate voltages applied to the dummy transistor to optimize the compensation effect. By controlling the rate of change of gate voltages, the circuit maintains effective clock feedthrough cancellation while allowing for faster switching operations, thus resolving the conflict between switching speed and feedthrough effects

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces the effect of clock feedthrough, leading to improved conversion accuracy and reduced error voltages in SAR-ADCs by ensuring equal charge movement in main and dummy transistors, thereby enhancing the overall performance of semiconductor integrated circuits.

Implementation Method 1

a first main MOS transistor MM1 having a first polarity... a first dummy MOS transistor MD1 having the first polarity

Methodology Applied

Scientific EffectMOS effect:

Implementation Method 2

switch control circuit that supplies a first voltage according to a control signal to a gate of the first main MOS transistor, supplies a second voltage opposite in phase to the first voltage to a gate of the first dummy MOS transistor, and is configured to be capable of adjusting a slew rate of each of the first voltage and the second voltage

Methodology Applied

Scientific EffectSlew rate control:

Data Source

PatentUS20240405775A1Semiconductor integrated circuit including MOS switch

Publication Date: 2024.12.05 ROHM CO LTD

AI summary

Provided is a semiconductor integrated circuit including a metal-oxide-semiconductor (MOS) switch, in which the MOS switch includes a first main MOS transistor having a first polarity, a first dummy MOS transistor having the first polarity and having opposed ends each connected to a first end of the first main MOS transistor, and a switch control circuit that supplies a first voltage according to a control signal to a gate of the first main MOS transistor, supplies a second voltage opposite in phase to the first voltage to a gate of the first dummy MOS transistor, and is configured to be capable of adjusting a slew rate of each of the first voltage and the second voltage.