Symmetric MOS Switch Layout for High-Linearity Mixers
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Solution Overview
Problem
The linearity of mixers in electronic communications systems, particularly in microwave wireless communications and radar systems, is poor due to ineffective suppression of interfering signals at high radio frequency amplitudes, which affects the mixer's performance.
Innovation Solution
A switch circuit and mixer design utilizing symmetrically arranged MOS transistors with equal gate parasitic capacitance, achieved by ensuring all MOS transistors have gates connected to ports with leads of equal length and symmetrically arranged to reduce parasitic capacitance inconsistencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MOS transistors are arranged in a conventional layout, then the circuit can be implemented, but the gate parasitic capacitances of different MOS transistors are inconsistent, resulting in poor linearity
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing the circuit layout to achieve symmetry in parasitic characteristics. Specifically, MOS transistors are arranged such that their gate leads have equal lengths and follow symmetric paths, making the parasitic capacitance characteristics uniform across all transistors. This symmetric arrangement compensates for the natural asymmetry in conventional layouts, resolving the linearity issue caused by inconsistent gate parasitic capacitances.
Solution Approach 2:
The patent implements equipotentiality by ensuring that all gate leads of the MOS transistors have equal lengths and are routed through symmetric paths. This design approach equalizes the electrical characteristics of all transistor gates, creating uniform parasitic capacitance values. By making all gate connections equivalent in terms of parasitic effects, the circuit achieves consistent linearity performance across all transistor elements.
2Ease of manufacture
If the lead lengths from MOS transistor gates to ports are unequal, then the circuit layout is simpler, but the gate parasitic capacitances differ, degrading mixer linearity
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing the circuit layout to achieve symmetry in parasitic characteristics. Specifically, MOS transistors are arranged such that their gate leads have equal lengths and follow symmetric paths, making the parasitic capacitance characteristics uniform across all transistors. This symmetric arrangement compensates for the natural asymmetry in conventional layouts, resolving the linearity issue caused by inconsistent gate parasitic capacitances.
Solution Approach 2:
The patent changes the geometric parameter of lead lengths from unequal to equal, and adjusts the routing paths to be symmetric. By modifying these physical dimensions and configurations, the parasitic capacitance parameters of all MOS transistor gates are made consistent. This parameter adjustment directly improves linearity while maintaining manufacturing feasibility through systematic layout design.
3Manufacturing precision
If MOS transistors are symmetrically arranged with equal lead lengths, then gate parasitic capacitances are consistent improving linearity, but the circuit layout becomes more complex
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing the circuit layout to achieve symmetry in parasitic characteristics. Specifically, MOS transistors are arranged such that their gate leads have equal lengths and follow symmetric paths, making the parasitic capacitance characteristics uniform across all transistors. This symmetric arrangement compensates for the natural asymmetry in conventional layouts, resolving the linearity issue caused by inconsistent gate parasitic capacitances.
Solution Approach 2:
The patent merges the layout design of multiple MOS transistors into a unified symmetric structure. By combining the transistors into a symmetric arrangement where all gate leads originate from common points and extend equally, the design achieves consistent parasitic characteristics. This merging approach simplifies the overall layout complexity by creating a regular, repeating pattern rather than treating each transistor independently.
Data Source
AI summary
A switch circuit, a mixer, and an electronic device, where the switch circuit includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, both a gate of the first MOS transistor and a gate of the fourth MOS transistor are connected to a first port, and both a gate of the second MOS transistor and a gate of the third MOS transistor are connected to a second port; and a lead between the gate of the first MOS transistor and the first port, a lead between the gate of the second MOS transistor and the second port, a lead between the gate of the third MOS transistor and the second port, and a lead between the gate of the fourth MOS transistor and the first port all have an equal length. In this way, linearity is relatively high.