Symmetrical MOS Switch Layout for Mixer Linearity
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Solution Overview
Problem
Existing mixers in electronic communications systems suffer from poor linearity, particularly due to inconsistent gate parasitic capacitances of MOS transistors, which are not effectively suppressed, leading to interference and reduced performance.
Innovation Solution
The proposed switch circuit and mixer designs utilize symmetrical arrangements of MOS transistors with equal gate lead lengths and parasitic capacitances, ensuring consistent gate parasitic capacitances by aligning and connecting transistors in a symmetrical layout, reducing lead lengths, and using separate deep N-wells for transistor groups to improve isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If MOS transistors are arranged with different gate lead lengths in conventional mixer designs, then routing flexibility is improved, but gate parasitic capacitances become inconsistent leading to poor linearity
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately enforces symmetry in the gate lead lengths of MOS transistors M1-M4, making them all equal despite the asymmetric functional requirements of the mixer circuit. This symmetric design ensures consistent gate parasitic capacitances (Cgs and Cgd) across all transistors, directly improving linearity and reducing second-order distortion while maintaining routing flexibility through the symmetric layout structure.
2Manufacturing precision
If gate lead lengths are equalized to improve linearity, then gate parasitic capacitances become consistent, but circuit layout complexity increases
Solution Approach 1:
The patent applies local quality by making specific local modifications to the gate lead lengths of individual MOS transistors. Rather than changing the entire circuit layout, it focuses on equalizing only the gate lead lengths (L1-L4) to be equal, while allowing other parts of the circuit to maintain their functional asymmetries. This localized approach improves linearity without requiring complete redesign of the entire circuit layout.
3Manufacturing precision
If symmetrical layout with equal gate lead lengths is used, then linearity is improved, but isolation between transistor groups may be reduced
Solution Approach 1:
The patent introduces deep N-wells as intermediary structures between the MOS transistor groups. These deep N-wells act as isolation barriers that prevent interference and crosstalk between the transistor groups while allowing the gate leads to be routed symmetrically. The deep N-wells serve as a physical mediator that maintains both the symmetrical layout for linearity and the isolation for reducing harmful interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the linearity of the mixer by ensuring consistent parasitic capacitances and reduced interference, thereby improving signal processing efficiency and reducing costs.
Implementation Method 1
all the MOS transistors have a same gate parasitic capacitance
Data Source
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AI summary
Embodiments of this application disclose a switch circuit, a mixer, and an electronic device. The switch circuit includes a first metal oxide semiconductor MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, both a gate of the first MOS transistor and a gate of the fourth MOS transistor are connected to a first port, and both a gate of the second MOS transistor and a gate of the third MOS transistor are connected to a second port; and a lead between the gate of the first MOS transistor and the first port, a lead between the gate of the second MOS transistor and the second port, a lead between the gate of the third MOS transistor and the second port, and a lead between the gate of the fourth MOS transistor and the first port all have an equal length. In this way, linearity is relatively high.