MOS Threshold Voltage Adjustment Using Process Mapping
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Solution Overview
Problem
The continuous decrease in feature sizes of semiconductor structures complicates the adjustment of threshold voltage in CMOS transistors due to increased difficulty in forming work function layers, particularly with high-k gate dielectric materials, leading to challenges in achieving the required threshold voltage intervals for NMOS and PMOS devices.
Innovation Solution
A process manufacturing method that determines the type of MOS device and corresponding threshold voltage interval, using pre-configured mapping relationships to establish a threshold voltage adjustment process, which combines adjustment processes such as electric dipole layer formation, work function layer formation, and plasma treatment to achieve the desired threshold voltage within specific intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional silicon dioxide gate dielectric material is replaced with high-k gate dielectric material, then leakage current is reduced, but threshold voltage adjustment becomes more difficult
Solution Approach 1:
The patent segments the gate dielectric layer into multiple layers: a lower gate dielectric layer (first material, e.g., silicon dioxide) and an upper gate dielectric layer (second material with higher dielectric constant, e.g., high-k material). This segmentation allows the lower layer to provide good interface characteristics and the upper layer to provide high capacitance, thereby reducing leakage current while maintaining threshold voltage adjustability through the work function layer.
Solution Approach 2:
The patent uses composite gate dielectric structure combining two different materials with complementary properties. The first gate dielectric material provides excellent interface quality with the semiconductor substrate, while the second high-k material provides higher dielectric constant. This composite structure achieves both low leakage current and controllable threshold voltage through work function layer formation.
2Manufacturing precision
If different work function layer materials are used for PMOS and NMOS devices, then threshold voltage requirements are met, but process complexity increases
Solution Approach 1:
The patent makes the work function layer universal by using the same material (e.g., titanium nitride) for both PMOS and NMOS devices. The layer serves multiple functions: it adjusts threshold voltage for both device types and acts as a barrier layer preventing boron diffusion. By making the work function layer multi-functional and identical for both device types, process complexity is reduced while still meeting different threshold voltage requirements through selective removal or modification.
Solution Approach 2:
The patent applies local quality by selectively removing or modifying the work function layer in specific regions. The work function layer is formed uniformly across the substrate but then selectively removed in NMOS regions or selectively modified to achieve different threshold voltage characteristics for PMOS and NMOS devices, thereby maintaining material uniformity while achieving local functional differentiation.
Data Source
AI summary
A process manufacturing method, a method for adjusting a threshold voltage, a device, and a storage medium are provided. One form of a process manufacturing method includes: determining a type of to-be-formed MOS device and a corresponding threshold voltage interval; obtaining, according to a MOS device type and the corresponding threshold voltage interval, a corresponding threshold voltage adjustment process by querying a pre-configured first mapping relationship of the threshold voltage interval and a second mapping relationship of the threshold voltage interval; and establishing a process flow according to the corresponding threshold voltage adjustment process, the first mapping relationship being a mapping relationship between the threshold voltage interval and the MOS device type; and the second mapping relationship being a correspondence between the threshold voltage interval in the first mapping relationship and a threshold voltage adjustment process formed by at least one adjustment process selected from a preset process flow, the threshold voltage adjustment process causing a threshold voltage to be in the corresponding threshold voltage interval under the action of a total threshold voltage offset. According to the present disclosure, the difficulty in adjusting the threshold voltage is reduced.