MOS Device Threshold Adjustment via Spacer Width Adaptation
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Solution Overview
Problem
The challenge in manufacturing integrated circuits is to maintain proper transistor performance with reduced gate lengths, particularly in controlling channel regions and managing leakage currents, while also adjusting threshold voltages to optimize performance without increasing static power consumption.
Innovation Solution
The solution involves adapting the width of sidewall spacers and varying tilt angles during dopant implantation to increase Miller capacitance, allowing for efficient adjustment of threshold voltages without additional implantation techniques, thereby enhancing transistor performance and reducing static leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to increase packing density and performance, then the number of transistor elements and operating speed are enhanced, but short channel effects occur resulting in reduced controllability of the channel region and increased leakage currents
Solution Approach 1:
The source and drain regions are segmented into multiple zones with different dopant concentrations: a lightly-doped extension region adjacent to the channel and a heavily-doped region beneath the gate electrode. This segmentation allows the extension region to provide channel control while the heavily-doped region maintains conductivity, resolving the contradiction between reduced gate length and channel controllability.
Solution Approach 2:
Different regions of the source and drain are given different local properties: the extension region has low dopant concentration for channel control, while the region beneath the gate has high dopant concentration for conductivity. This local quality differentiation enables simultaneous achievement of channel controllability and low resistance contact.
2Reliability
If ion implantation is performed to achieve high dopant concentration for shallow junctions, then conductivity is improved, but heavy damage is generated in the crystal structure requiring additional anneal cycles
Solution Approach 1:
Instead of performing a single high-dose implantation that causes severe damage, the process uses multiple implantation steps with progressively higher doses. Each step introduces dopants with manageable damage levels, and the cumulative effect achieves the desired high concentration without requiring excessive annealing.
Solution Approach 2:
Low-dose implantation is performed first to create the extension region before high-dose implantation. This preliminary action establishes a dopant profile that guides subsequent processing and reduces the need for extensive annealing in later steps, as the initial doping provides a foundation for the final profile.
3Productivity
If threshold voltage is reduced to maintain high saturation current at reduced gate voltage, then performance is improved, but static leakage currents increase contributing to power consumption
Solution Approach 1:
The source and drain regions are differentiated into zones with different dopant concentrations: the extension region with low concentration reduces leakage currents by improving junction control, while the heavily-doped region beneath the gate maintains high saturation current. This local quality differentiation resolves the contradiction between performance and power consumption.
4Reliability
If multiple implantation techniques are used to adjust threshold voltages, then transistor performance is optimized, but process complexity increases
Solution Approach 1:
The formation of extension regions and adjustment of threshold voltages are merged into a unified implantation sequence. The same ion implantation process that creates the shallow junctions also establishes the dopant gradients needed for threshold voltage control, eliminating the need for separate implantation steps and reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases Miller capacitance and adjusts threshold voltages, leading to improved transistor performance with reduced static leakage currents and power consumption, while maintaining process complexity comparable to conventional strategies.
Implementation Method 1
forming a spacer layer above a first structure formed above a first active region of a semiconductor device. The spacer layer is also formed above a second structure
Implementation Method 2
performing an implantation sequence on the basis of the first and second structures and the first and second spacer elements to form drain and source regions
Data Source
AI summary
Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.