MOS Thyristor Gate Structure for 0 V Turn-Off and Uniform Switching
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Solution Overview
Problem
The MOS controlled thyristor device faces challenges in improving turn-on/turn-off characteristics and uniformity of operation, particularly in turning off at 0 V, which affects the design and efficiency of the gate driving circuit.
Innovation Solution
The device incorporates a substrate with specific doping patterns and conductive types, including a first doping pattern with a segmented shape and a threshold voltage control layer, to create distinct on-FET and off-FET channels, enabling turn-on at a predetermined gate voltage and turn-off at 0 V, thereby enhancing turn-on/turn-off characteristics and operational uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MOS controlled thyristor structure is used, then the device can be turned on at a predetermined gate voltage, but it cannot be turned off at 0 V and the turn-on/turn-off characteristics are poor
Solution Approach 1:
The gate electrode is divided into a first gate electrode and a second gate electrode, which are positioned at different locations and perform different functions. The first gate electrode controls turn-on at a predetermined voltage, while the second gate electrode enables turn-off at 0 V, thus segmenting the gate control function to resolve the contradiction between reliable switching and ease of operation.
Solution Approach 2:
A doping pattern is introduced as an intermediary element between the gate electrodes and the channel region. This doping pattern modifies the electrical characteristics of the channel, enabling the device to respond appropriately to 0 V gate signals for turn-off while maintaining proper turn-on characteristics through the gate electrodes.
2Ease of operation
If the gate structure is simplified for easy operation, then the device can be operated easily, but the turn-on/turn-off characteristics and operational uniformity deteriorate
Solution Approach 1:
The gate system is segmented into two independent gate electrodes that can be controlled separately. This segmentation allows the gate driving circuit to apply different voltages to different gate electrodes, achieving both ease of operation through independent control and reliable turn-on/turn-off characteristics through coordinated voltage application.
Solution Approach 2:
Different regions of the gate structure are given different electrical characteristics through the doping pattern. The doping pattern creates localized changes in the channel region that enable uniform operational characteristics across the device while maintaining simple gate control through the two gate electrodes.
3Reliability
If a dual gate electrode structure with doping pattern is implemented, then turn-on/turn-off characteristics improve, but the device complexity increases
Solution Approach 1:
The gate is segmented into two electrodes with distinct functions, which improves turn-on/turn-off characteristics. The segmentation is implemented in a way that leverages standard semiconductor fabrication techniques, balancing the improved reliability against the increased structural complexity.
Solution Approach 2:
The dual gate electrode structure with doping pattern serves multiple functions: it enables turn-on at predetermined voltage, turn-off at 0 V, and maintains operational uniformity. This multi-functionality justifies the increased device complexity by consolidating multiple critical functions into a single integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the turn-on/turn-off performance and uniformity of the MOS controlled thyristor device, allowing for efficient gate driving circuit design and stable operation by ensuring smooth current flow and proper threshold voltage adjustment.
Implementation Method 1
a first doping pattern (110) having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region (105)... the first doping pattern (110) is interposed between the upper base region (104) and the first doped region (106)
Implementation Method 2
A MOS controlled thyristor (MCT) is a device that integrates a MOS gate pattern (gate) with a thyristor having a PNPN structure to control turn-on/turn-off of the thyristor through a gate voltage
Implementation Method 3
a thyristor having a PNPN structure to control turn-on/turn-off of the thyristor through a gate voltage
Data Source
AI summary
A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.