MOS T/R Switch Circuit With Floating Gate Tracking for Low-Noise Ultrasound
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Solution Overview
Problem
Existing transmission/reception switch circuits for ultrasonographs face challenges in maintaining low noise and preventing erroneous operations over a wide frequency band, especially when signal potentials change, leading to potential element destruction and crosstalk issues.
Innovation Solution
A switch circuit configuration with a main switch comprising two MOS transistors and a voltage control circuit that synchronizes the common gate potential with the common source potential, using latch circuits and a floating voltage generator to control the main switch's on/off states, thereby minimizing noise and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the main switch is turned on by charging capacitors C1 and Cgs to Vdc, then the on-state can be maintained without steady current, but the on-state becomes unstable and difficult to maintain for extended periods due to gate leakage and crosstalk
Solution Approach 1:
The patent introduces a feedback mechanism where the holding circuit continuously monitors the switch state and provides corrective control signals to maintain the desired state. The holding circuit uses the state of the main switch to control the gates of M3 and M4, creating a regenerative feedback loop that reinforces the on-state or off-state against disturbances like gate leakage and crosstalk.
Solution Approach 2:
The patent implements protective measures in advance by designing the holding circuit to preemptively counteract potential state changes. The circuit structure with M3 and M4 configured as complementary switches provides built-in protection against gate leakage and crosstalk before they can cause erroneous switching, cushioning the system against these harmful effects.
2Device complexity
If the control signal is sent directly from the holding circuit to M1 and M2, then switching control is simple, but the holding circuit state can change due to gate leakage or signal crosstalk causing erroneous operations
Solution Approach 1:
The patent introduces an intermediary control mechanism where the holding circuit does not directly control M1 and M2, but instead controls M3 and M4 which in turn control the main switch. This intermediary layer (M3 and M4 acting as buffer switches) isolates the holding circuit from direct exposure to leakage and crosstalk effects, preventing erroneous state changes while maintaining control functionality.
3Speed
If negative high voltage is applied from GND via input/output terminal, then the common source voltage quickly follows due to parasitic diode, but the common gate voltage cannot instantaneously follow causing high voltage to be applied to C1 and MOS transistors potentially breaking elements
Solution Approach 1:
The patent implements protective measures in advance by configuring M3 and M4 as complementary switches that prevent excessive voltage from reaching C1 and the MOS transistors. The holding circuit structure provides built-in protection against voltage spikes and transient overvoltages before they can cause element breakdown, cushioning the sensitive components against these harmful effects.
Solution Approach 2:
The patent introduces M3 and M4 as intermediary protective elements between the input/output terminal and the sensitive components (C1 and MOS transistors). These intermediary switches control the voltage transmission path, preventing direct coupling of high-voltage transients to vulnerable components while allowing normal signal passage during legitimate operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-noise, wide-band signal transmission without erroneous switch operations or element damage, even with varying signal potentials, by maintaining the main switch's state effectively and reducing parasitic capacitance.
Implementation Method 1
a main switch having a first MOS transistor, to a drain terminal of which a first input/output terminal is connected, and a second MOS transistor, to a drain terminal of which a second input/output terminal is connected
Implementation Method 2
when a negative high voltage (−HV) is applied from GND via an input/output terminal, the voltage of the common source S quickly follows the applied voltage thanks to the parasitic diode M1
Implementation Method 3
C1 in the latch circuit and capacitance Cgs between the gate and source of each of M1 and M2 in the main switch circuit are charged up to around Vdc
Data Source
AI summary
A T/R switch applicable to an ultrasonograph and capable of transmitting a signal reflected from a living body over a wide band with low noise without causing erroneous operation of the switch or element destruction even when the potential of a transmission signal or reflected signal changes includes: a common source terminal commonly and serially coupling the source terminals of two MOS transistors; a common gate terminal commonly coupling the gate terminals of the two MOS transistors; a main switch, the drain terminals of which are connected to input/output terminals; and a floating voltage circuit which is connected to the common gate terminal and common source terminal, makes the common gate terminal potential follow, in phase, variation in the common source terminal potential, and sends a signal to turn the switch on or off to the common gate terminal.