Metal Oxide Transistor Channel Width Ratio via Vertical Electrode Segmentation
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Solution Overview
Problem
Conventional thin film transistors with metal oxide semiconductor channel layers face issues such as over-etching during manufacturing, low channel width/length ratio, and difficulty in increasing this ratio due to same-plane source and drain electrode formation processes.
Innovation Solution
The semiconductor device incorporates a metal oxide thin film transistor structure with a channel layer covered by a passivation layer and contact holes in a second conductive layer, allowing source and drain electrodes to be formed in different processes, increasing the channel width/length ratio and preventing over-etching, with optional overcoat layers to reduce stray capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source electrode and drain electrode are formed by the same manufacturing process at the same plane, then the manufacturing process is simple, but it is difficult to increase the channel width/length ratio
Solution Approach 1:
The source and drain electrodes are segmented into different manufacturing processes and positioned at different planes. The first conductive layer forms the source electrode while the third conductive layer forms the drain electrode, allowing independent optimization of each electrode's position and formation process to achieve higher channel width/length ratio
Solution Approach 2:
The invention transitions from a two-dimensional same-plane electrode configuration to a three-dimensional structure where the source and drain electrodes are positioned at different vertical planes. The second conductive layer with inner opening and the passivation layer with contact hole enable this vertical separation, allowing the channel to extend in the vertical dimension and increase the effective channel width/length ratio
2Reliability
If the channel layer is made of metal oxide semiconductor, then the mobility and reliability are improved, but the channel layer can be over-etched during etching the source and drain electrodes
Solution Approach 1:
The second conductive layer with inner opening is formed before the channel layer deposition. This preliminary structure defines the exact region where the channel layer will be deposited, ensuring that subsequent etching processes for the source and drain electrodes will not affect the channel layer since it is already positioned within the protected inner opening region
Solution Approach 2:
The passivation layer acts as an intermediary protective barrier between the etching liquid used for forming source/drain electrodes and the metal oxide channel layer. The contact hole in the passivation layer provides a controlled pathway that prevents direct exposure of the channel layer to etching chemicals, thereby preventing over-etching while maintaining manufacturing precision
Data Source
AI summary
There is provided a semiconductor device including a first conductive layer, an insulating layer, a second conductive layer, a channel layer, a passivation layer and a third conductive layer. The insulating layer covers the first conductive layer. The second conductive layer is formed on the insulating layer and has an inner opening. The channel layer is formed on the inner opening of the second conductive layer to fully cover the inner opening. The passivation layer is formed upon the channel layer to cover the channel layer and has a contact hole inside the inner opening of the second conductive layer. The third conductive layer is formed in the contact hole.