MOS Transistor Circular Planar Junction for Breakdown Voltage

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Solution Overview

Problem

High voltage MOS transistors face reduced drain breakdown voltage due to junction curvature effects, and existing methods to counterbalance this often require additional processing steps and masks, increasing costs.

Innovation Solution

A MOS transistor design with a circular planar PN junction having a surface curvature pointing towards the drain region, which relaxes electrical field intensity and increases avalanche breakdown voltage without additional processing steps or masks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a linear planar PN junction is formed in conventional MOS transistor design, then the device structure is simple and fabrication is easy, but the junction curvature effect decreases the avalanche breakdown voltage

Engineering Contradiction:
Improvefabrication simplicityVSAvoiddrain breakdown voltage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies curvature by forming a circular planar PN junction instead of a linear one. The circular drain region intersects with the adjustment implant layer to create a curved junction geometry. This curvature redistributes the electrical field, reducing peak field intensity at the junction and increasing the avalanche breakdown voltage by up to 24%, while maintaining fabrication simplicity through standard circular photolithography patterns.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Reliability

If supplementary processing steps and masks are added to counterbalance junction curvature effect, then the drain breakdown voltage can be improved, but the manufacturing cost and device complexity increase

Engineering Contradiction:
Improvedrain breakdown voltageVSAvoidprocessing steps and masks
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the geometric parameter of the PN junction from linear to circular, which fundamentally alters the electrical field distribution. This parameter change achieves higher breakdown voltage without requiring additional processing steps or masks. The circular geometry is formed using standard photolithography patterns already present in the fabrication process, thus improving reliability while avoiding increased device complexity.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If the junction curvature effect is not addressed, then the manufacturing process remains simple and cost-effective, but hot carrier injection effects increase and reduce device performance

Engineering Contradiction:
Improvemanufacturing cost-effectivenessVSAvoidhot carrier injection effects
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The circular planar PN junction geometry redistributes the electrical field more uniformly, reducing peak field intensity at the junction. This reduced peak field intensity decreases hot carrier generation through impact ionization, thereby reducing hot carrier injection effects that can degrade device performance. The solution maintains cost-effectiveness by using standard circular fabrication patterns without requiring additional processing steps.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The circular planar PN junction design effectively increases drain breakdown voltage by up to 24% and reduces hot carrier injection effects, maintaining high transconductance while avoiding costly supplementary processing.

Implementation Method 1

the drain breakdown voltage of the NMOS transistor 100 is determined by an avalanche breakdown voltage of the linear planar PN junction 118

Methodology Applied
Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS7893507B2Metal oxide semiconductor (MOS) transistors with increased break down voltages and methods of making the same
Publication Date: 2011.02.22 O2 MICRO INT LTD
  • US7893507B2 patent drawing
  • US7893507B2 patent drawing
  • US7893507B2 patent drawing

AI summary

A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction.