MOS Transistor Degradation Clock Circuit for Low Power Timekeeping

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Solution Overview

Problem

Conventional clock circuits for integrated circuits require significant power, have a large footprint, and high manufacturing costs, making them unsuitable for compact and cost-sensitive applications like smart cards.

Innovation Solution

A clock circuit based on a transistor with irreversible degradation induced by stress, measuring parameters like drain current to calculate elapsed time, which includes a temperature measurement stage and memory to store variation laws, allowing for low power consumption and compact design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional clock circuits (quartz crystal, mechanical counters) are used, then time measurement function is achieved, but power consumption becomes too high

Engineering Contradiction:
Improvepower consumptionVSAvoidtime measurement function
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent replaces conventional mechanical/electrical clock mechanisms (quartz crystals, mechanical counters) with a transistor-based system that uses electrical degradation phenomena. Instead of mechanical vibration or electrical oscillation, time is measured through the irreversible degradation of transistor parameters, eliminating the need for continuous power supply to maintain oscillation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent exploits changes in transistor parameters (threshold voltage, drain current, transconductance) over time due to degradation mechanisms like NBTI and hot carrier injection. By monitoring these parameter changes, the system measures elapsed time without requiring the transistor to remain in a stable operating state, thus reducing power consumption while maintaining measurement function.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If conventional clock circuits are used, then time measurement function is achieved, but footprint area becomes too large

Engineering Contradiction:
Improvefootprint areaVSAvoidtime measurement function
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent extracts the time measurement function from complex mechanical/electrical clock mechanisms and implements it using a simple transistor degradation model. By removing unnecessary components (oscillators, counters, power regulation circuits) and keeping only the essential degradation-monitoring elements, the footprint is dramatically reduced while maintaining the core time measurement capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The transistor serves multiple functions: it is both the timing element (through degradation) and the measurement element (through parameter monitoring). This multi-functionality eliminates the need for separate clock generation and time measurement components, reducing overall circuit footprint while ensuring reliable time measurement.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If conventional clock circuits are used, then time measurement function is achieved, but manufacturing cost becomes too high

Engineering Contradiction:
Improvemanufacturing costVSAvoidtime measurement function
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent uses a transistor that is intentionally degraded over time to measure elapsed time. The transistor does not need to be preserved or restored, and its degradation is the measurement mechanism itself. This approach uses inexpensive, replaceable components rather than expensive, precision-maintained clock mechanisms, reducing manufacturing costs while ensuring reliable time measurement.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The transistor's natural degradation process serves the time measurement function without requiring external control or maintenance. The degradation occurs automatically under bias stress, and monitoring this self-generated change provides the time measurement, eliminating the need for complex control circuits and reducing manufacturing complexity and cost.

Inventive Principle:
Principle #25Self-service

4Use of energy by moving object

If transistor degradation is used for time measurement, then power consumption is reduced, but measurement precision becomes challenging

Engineering Contradiction:
Improvepower consumptionVSAvoidtime measurement precision
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent implements feedback by continuously monitoring transistor parameters (threshold voltage, drain current, transconductance) and using this information to calculate elapsed time. The system compensates for variations in degradation rate by referencing stored calibration data and adjusting measurements accordingly, maintaining precision while keeping power consumption low through periodic rather than continuous measurement.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary calibration by storing the relationship between transistor parameters and elapsed time in memory before actual time measurement begins. This pre-established reference data allows the system to accurately interpret parameter changes during operation, ensuring measurement precision without requiring complex real-time calculations or high power consumption.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a simple, compact, and low-power clock circuit capable of accurately measuring time with minimal power consumption and reduced manufacturing costs, suitable for integrated circuits.

Implementation Method 1

a first circuit to induce degradation of the transistor as a function of time. The degradation is at least partially irreversible

Methodology Applied
Scientific EffectTransistor degradation:

Implementation Method 2

a temperature measurement stage to measure the temperature in the clock circuit

Methodology Applied
Scientific EffectTemperature measurement:

Data Source

PatentUS7660691B2Clock circuits and counting values in integrated circuits
Publication Date: 2010.02.09 STMICROELECTRONICS (CROLLES 2) SAS
  • US7660691B2 patent drawing
  • US7660691B2 patent drawing
  • US7660691B2 patent drawing

AI summary

A clock circuit for an integrated circuit having at least one MOS transistor. The clock circuit includes a first circuit for inducing a degradation of the transistor as a function of time and circuit for measuring a parameter of the transistor that reflects a lowering of the performance of the transistor resulting from the degradation. This also includes a method of generating a counting value of clock circuit by inducing continuous degradation of an MOS transistor. The method could include measuring a parameter of transistor, reflecting a lowering of performance of transistor resulting from the degradation. The method could also include measuring the temperature and calculating the counting value of the clock from the value of the parameter, from the measured temperature and from a law of variation of the parameter as a function of time and temperature.