MOS Transistor ESD Protection with Distributed Silicide Contacts
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Solution Overview
Problem
Conventional ESD protection devices in semiconductor chips face challenges in efficiently discharging ESD stress current due to concentrated current paths, leading to reduced performance and increased risk of device destruction as chip sizes shrink.
Innovation Solution
The ESD protection device incorporates a metal-oxide semiconductor transistor with strategically placed silicides on the source and drain areas, forming wider current paths and optimized metal connections to facilitate efficient discharge of ESD stress current, including a multi-finger structure and varying silicide sizes to reduce resistance and spread current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If contacts are arranged only at some areas of the source and drain with silicides formed around the contacts to reduce contact resistance, then contact resistance is decreased, but current paths are formed only between facing contacts with minimum distance, causing ESD stress current to concentrate on specific contacts
Solution Approach 1:
The source and drain areas are segmented into multiple regions with multiple contacts distributed across each area. Instead of having contacts only at specific locations, the source area includes first, second, and third contacts, and the drain area includes fourth, fifth, and sixth contacts. This segmentation distributes the current paths across multiple contacts rather than concentrating them at a single location, resolving the contradiction between reducing contact resistance and preventing current concentration.
Solution Approach 2:
Silicides are formed around each contact location (first through sixth contacts) with varying configurations. The silicide around the first contact has a first area, the silicide around the second contact has a second area, and so on. This local quality approach allows each contact region to be optimized for low resistance while the overall distribution of contacts prevents current concentration, simultaneously achieving low contact resistance and high reliability.
2Area of stationary object
If the electric power line and the ground line are arranged over the GGNMOS for reducing area, then chip area is reduced, but current paths are limited to only between facing contacts with minimum distance
Solution Approach 1:
The contact arrangement transitions from a one-dimensional linear arrangement (contacts only at facing positions) to a two-dimensional distributed arrangement. The source area contains contacts at multiple positions (first, second, third contacts) and the drain area contains contacts at multiple positions (fourth, fifth, sixth contacts), creating current paths that extend in multiple directions rather than just between facing contacts. This dimensional expansion maintains compact area while improving current discharge efficiency.
3Manufacturing precision
If contacts are arranged within the drain and source areas with silicides formed around the contacts, then contact resistance is decreased, but ESD stress current concentrates on specific contacts causing easy destruction of the ESD protection device
Solution Approach 1:
The device structure is segmented into multiple contact regions with distributed contacts. The source area is divided into regions with first, second, and third contacts, and the drain area is divided into regions with fourth, fifth, and sixth contacts. This segmentation distributes the mechanical and electrical stress across multiple contact points rather than concentrating it at a single location, enhancing device durability while maintaining low contact resistance through silicide formation at each contact.
Solution Approach 2:
The silicide area parameters are varied across different contact locations. The silicide around the first contact has a first area, the silicide around the second contact has a second area, and so on through the sixth contact. By changing the silicide area parameters at different locations, the contact resistance is optimized at each point while the overall distribution pattern prevents stress concentration, thereby improving device strength and durability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the ability to discharge ESD stress current efficiently, improving the ESD protection level by reducing contact resistance and spreading the current across a broader area, thus protecting internal circuits from damage.
Implementation Method 1
silicides are formed around the contacts to decrease a contact resistance
Data Source
AI summary
An Electro-Static Discharge (ESD) protection device is provided. The ESD protection device includes a metal-oxide semiconductor (MOS) transistor, including a source area having a surface on which a first silicide is formed, the source area including a source connecting area including a first connecting portion formed on the first silicide, and a source extension area, a gate arranged in parallel with the source area, and a drain area arranged in parallel with the source area and the gate, the drain area having a surface on which a second silicide is formed, the drain area including a drain connecting area formed opposite the source extension area, the drain connecting area including second connection portion formed on the second silicide, and a drain extension area formed opposite the source connecting area.