MOS Transistor With Extended Source Drain Active Areas
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Solution Overview
Problem
The narrow width effect and short channel effect in semiconductor transistors lead to increased threshold voltage and reduced current driving performance, particularly affecting PMOS and NMOS transistors, where adjustments to one type of transistor often deteriorate the performance of the other.
Innovation Solution
A MOS transistor design with additional active areas of larger width than the channel width, added to both the source and drain areas, maintains the channel width and length while enhancing current driving performance without modifying the manufacturing process or introducing new steps, thereby optimizing the performance of both PMOS and NMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel width of a transistor is reduced to improve integration density, then the threshold voltage increases due to narrow width effect, but the current driving performance deteriorates
Solution Approach 1:
The patent extends the active area in the lateral dimension beyond the channel width, creating additional current paths at the source and drain regions. This dimensional extension allows more carriers to flow without increasing the channel width, thus improving current driving performance while maintaining narrow channel dimensions for high integration density
Solution Approach 2:
The active area is segmented into multiple regions: the channel region of width W0, and additional source/drain active areas of width W1 where W1 > W0. This segmentation creates multiple parallel current paths, with the extended active areas providing additional carrier injection and collection regions that enhance overall current drive capability
2Quantity of substance
If the channel width is reduced to increase integration density, then the threshold voltage increases, but the transistor performance for both PMOS and NMOS cannot be simultaneously enhanced
Solution Approach 1:
The patent applies different width characteristics to different regions: the channel maintains narrow width W0 for high integration density and appropriate threshold voltage control, while the source and drain active areas are extended to width W1 > W0. This local quality differentiation allows each region to fulfill its specific function optimally
Solution Approach 2:
By extending the active area width in the lateral dimension at the source and drain regions, the patent creates additional current paths that enhance both PMOS and NMOS performance simultaneously without affecting the channel width that determines integration density
Data Source
AI summary
Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.