MOS Transistor Drive Current via Gate Amorphization
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Solution Overview
Problem
Current semiconductor manufacturing techniques face limitations in increasing the drive current of MOS transistors due to the restricted magnitude of strain that can be induced in the channel region, and the challenge of increasing the amorphous content of gate electrodes without causing lattice damage or defects in the source/drain regions.
Innovation Solution
The method involves decoupling the dopant implantation process for gate electrodes from that of the source/drain regions, allowing for independent optimization of dopant species, energy, and dose to increase the amorphous content of gate electrodes while protecting the source/drain regions, followed by forming a stress memorization layer and annealing to induce strain in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopant implantation is performed to increase amorphous content of gate electrodes, then drive current increases, but lattice damage and defects occur in source/drain regions
Solution Approach 1:
The implantation process is segmented into two separate steps: first implanting dopants to create amorphous content in gate electrodes, then performing a second implantation to repair lattice damage in source/drain regions. This segmentation allows independent optimization of each implantation step to achieve both high drive current and minimal defects.
Solution Approach 2:
The first dopant implantation is performed as a preliminary action to increase amorphous content in gate electrodes before the main source/drain implantation. This preliminary action prepares the gate electrodes for subsequent processing while the protective layer prevents dopant penetration into source/drain regions during this initial step.
2Speed
If strain is induced in channel region to increase carrier mobility, then switching speed increases, but the magnitude of strain is restricted
Solution Approach 1:
The invention changes the physical state parameter of gate electrodes by increasing amorphous content through controlled dopant implantation. This parameter change enables greater strain induction in the channel region during subsequent annealing, thereby increasing carrier mobility and switching speed beyond what is achievable with conventional crystalline gate electrodes.
3Object-affected harmful factors
If protective layer is used to protect source/drain regions during implantation, then lattice damage is minimized, but additional process steps are required
Solution Approach 1:
A protective layer is introduced as an intermediary element between the dopant implantation process and the source/drain regions. This protective layer acts as a barrier that prevents dopant penetration into source/drain regions during the first implantation step, thereby protecting against lattice damage while allowing the gate electrodes to receive the full dopant dose needed to increase amorphous content.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the drive current of MOS transistors by enhancing the amorphous content of gate electrodes, reducing lattice strain, and minimizing defects in the source/drain regions, thereby improving transistor performance without compromising yield.
Implementation Method 1
The substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes
Implementation Method 2
A dopant is implanted into the exposed portions, but not into the source/drain regions, the implanting amorphizing the exposed portions
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.