MOS Transistor Gate Contact via Vertical Via Recesses
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Solution Overview
Problem
Existing methods for manufacturing MOS transistors face challenges in reducing transistor dimensions while avoiding short-circuits and parasitic capacitive coupling, particularly due to the need for lateral guards and the limitations in decreasing integration surface area.
Innovation Solution
The method involves forming amorphous regions on either side of the gate, etching these regions to create recesses, and depositing conductive material within these recesses to form source and drain regions, allowing vias to contact the gate and source/drain regions on the opposite side of the channel, thereby eliminating the need for conventional guards and reducing surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods with lateral guards are used, then short-circuit protection is improved, but transistor dimensions and integration surface area increase
Solution Approach 1:
The patent moves the contact points from the same plane as the gate to the opposite side of the channel region, utilizing the third dimension (vertical stacking) to resolve the spatial conflict between contact placement and gate proximity, thereby eliminating the need for lateral guards
Solution Approach 2:
The contact structure is nested within the vertical stack of the transistor, with contacts positioned beneath the channel region rather than beside it, allowing compact integration without lateral expansion
2Productivity
If transistor dimensions are decreased, then integration density is improved, but the risk of parasitic capacitive coupling increases
Solution Approach 1:
By positioning contacts on the opposite side of the channel from the gate, the patent increases the spatial separation between conductive elements, reducing parasitic capacitance while maintaining small lateral dimensions for high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a 35% reduction in the surface area of static-type RAM elementary cells, decreases the risk of parasitic capacitive coupling, and allows for smaller transistor dimensions without the need for lateral guards, improving integration density.
Implementation Method 1
totally etching the amorphous regions, whereby recesses are formed between the central region and the periphery
Implementation Method 2
depositing in the recesses only a conductive material capable of forming the source and drain regions of the transistor
Implementation Method 3
the step of forming the amorphous regions comprises the implantation of a dopant in the semiconductor layer in self-aligned fashion with respect to the gate
Data Source
AI summary
A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.