Multi-Channel MOS Transistor Gate Electrode Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in reducing thermal diffusion and resistance in source/drain regions of multi-channel MOS transistors, leading to short channel effects and increased parasitic capacitance, particularly when using bulk silicon substrates and isotropic etching processes.
Innovation Solution
A method involving the formation of an active channel pattern with alternately stacked gate and single crystalline silicon layers, followed by the growth of source/drain layers and the creation of gate trenches, which are then filled with a gate electrode that surrounds the channels, allowing for the removal of mask patterns and subsequent ion implantation into the source/drain regions after gate electrode formation, thereby minimizing thermal diffusion and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain regions are formed before gate electrode formation using conventional methods, then manufacturing process is simpler, but thermal diffusion increases and resistance remains high
Solution Approach 1:
The gate electrode is formed in advance before the source/drain regions are created. This preliminary action allows the gate electrode to serve as a mask during subsequent ion implantation, preventing thermal diffusion and reducing resistance in the source/drain regions while maintaining manufacturing simplicity.
Solution Approach 2:
The conventional sequence of forming source/drain regions before gate electrode is inverted. The gate electrode is formed first, then source/drain regions are created through ion implantation using the gate electrode as a mask, which resolves the thermal diffusion and resistance issues.
2Productivity
If channel length is shortened to increase device capacity, then device integration increases, but short channel effects worsen
Solution Approach 1:
The gate electrode is formed preliminarily before source/drain regions, creating a precise mask that defines the channel length accurately. This allows for shorter channel lengths to be achieved while maintaining control over short channel effects through precise ion implantation positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with low thermal diffusion and resistance, reduced junction capacitance, and improved operational speed by maintaining effective channel length and enabling uniform doping profiles, thus minimizing short channel effects.
Implementation Method 1
Silicon grows from a sidewall of the active channel pattern to form a source/drain layer
Implementation Method 2
Impurities are implanted into the source/drain regions to form source/drain regions
Data Source
AI summary
In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.