MOS Transistor Gate Formation on SOI Substrate
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Solution Overview
Problem
MOS transistors produced using SOI technology face challenges such as short channel effects due to the thin buried oxide layer, leading to reduced electrostatic coupling and excessive consumption of insulation material, as well as the formation of parasitic transistors from the gate material projecting over the SOI region.
Innovation Solution
A method involving ion implantation of germanium at the insulating region, followed by annealing to form a silicon-germanium alloy, allowing for selective etching and gate formation on a flat surface, thereby avoiding the attack on the buried oxide layer and eliminating parasitic transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching operations are performed during STI isolation region production, then the insulating region can be formed, but the thin buried oxide layer is attacked leading to excessive consumption of insulation material
Solution Approach 1:
The gate structure is formed before the STI isolation region etching operation. This preliminary formation of the gate on a flat surface prevents the etching process from attacking the thin buried oxide layer, as the gate structure serves as a protective element and the etching is confined to areas where the gate is not present.
Solution Approach 2:
The conventional sequence of operations is inverted: instead of forming the STI isolation region first and then the gate, the gate is formed first on a flat surface, and then the STI isolation region is created through selective etching. This reversal prevents oxide layer consumption.
2Ease of manufacture
If the gate material projects over the SOI region, then the gate can be formed, but parasitic transistors are created on the sides of the SOI
Solution Approach 1:
The gate structure is formed with different local properties: the gate material is deposited and patterned to extend laterally beyond the SOI region edges, creating an overlap region. This local extension is intentionally designed to prevent parasitic transistor formation by ensuring the gate electric field covers the entire SOI width, including edge regions where parasitic effects would otherwise occur.
Solution Approach 2:
The gate structure serves as an intermediary element that mediates between the source and drain regions. By extending the gate laterally beyond the SOI edges, it acts as an electric field barrier that prevents parasitic transistor formation at the SOI edges, where the gate material overlap creates a protective field configuration.
3Productivity
If the buried oxide layer thickness is reduced to achieve compact architecture, then electrostatic coupling between source and drain is reduced, but the gate must be formed on a non-flat surface
Solution Approach 1:
A flat surface is created preliminarily before gate formation by forming a planarization layer or adjusting the substrate surface. This preliminary flat surface allows subsequent gate deposition to occur on a uniform plane, ensuring precise gate formation even when the buried oxide layer is thin and the overall device architecture is compact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of transistors on thin buried oxide layers without attacking the insulation material and prevents the formation of parasitic transistors, allowing for improved control over transistor threshold voltage and reduced short channel effects.
Implementation Method 1
an ion implantation of germanium is carried out at the location of the future insulating region, the substrate is annealed so as to cause a localized transformation of the substrate into a silicon alloy- germanium
Implementation Method 2
the substrate is annealed so as to cause a localized transformation of the substrate into a silicon alloy- germanium
Implementation Method 3
an etching is performed at the location of the alloy zone of silicon-germanium so as to remove said alloy
Data Source
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AI summary
To fabricate a MOS transistor on a silicon-on-isothiazolinone (SOI) substrate placed on a buried oxide layer (BOX), the transistor is fabricated in an active region of the substrate delimited by an insulating region. The insulating region is formed, and a gate region, along with source and drain regions that define a channel, are created so that the gate region extends above the channel. The insulating region is created by localized formation of a zone of material suitable for selective etching relative to the silicon, selectively etching this material, and depositing a dielectric material at the etching site. Furthermore, the etching is performed after the gate region has been fabricated.