MOS Transistor Junction Control via Pre-Amorphization
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Solution Overview
Problem
Conventional methods for forming ultra shallow junctions in MOS transistors face limitations in depth control and lateral diffusion, leading to significant transient enhanced diffusion (TED) and short channel effects, especially as device scales reach 90-nm and smaller.
Innovation Solution
The method involves a pre-amorphization process followed by an oblique angle co-implantation of dopants like carbon, fluorine, or nitrogen, combined with rapid thermal annealing to form lightly doped drains, which reduces TED and lateral diffusion by regrowing the amorphized regions to a crystalline form, thereby controlling dopant diffusion and improving junction profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional low energy ion implantation is performed to form ultra shallow junctions, then junction depth is controlled, but transient enhanced diffusion (TED) effect and lateral diffusion occur causing poor threshold voltage roll-off
Solution Approach 1:
The patent performs pre-amorphization ion implantation before the main dopant implantation to create an amorphous silicon layer that will later be regrown. This preliminary action modifies the crystal structure to control subsequent dopant diffusion behavior, preventing TED effect while maintaining shallow junction depth
Solution Approach 2:
The patent introduces a regrown silicon layer as an intermediary between the amorphized region and the dopant source. This regrown layer acts as a diffusion barrier that controls dopant distribution, preventing both vertical deepening and lateral spread while maintaining the ultra shallow junction profile
2Productivity
If device scale is reduced to 90-nm and smaller to increase chip density, then manufacturing capability is improved, but short channel effect worsens due to poor threshold voltage roll-off
Solution Approach 1:
The patent applies different processing conditions to different regions of the device. The pre-amorphization and regrowth processes are selectively applied to create localized ultra shallow junctions in the drain regions, providing tailored dopant distribution that maintains threshold voltage control in scaled devices
Solution Approach 2:
The patent changes the physical and chemical parameters of the silicon lattice through pre-amorphization and regrowth. By controlling the amorphization depth, regrowth temperature, and dopant implantation parameters, the patent achieves precise control over junction depth and dopant distribution, enabling reliable operation at 90-nm scale
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the TED effect and short channel effect, maintaining a stable junction profile and improving threshold voltage roll-off characteristics, ensuring the MOS transistor operates within desired standards even at reduced scales.
Implementation Method 1
A pre-amorphization (PAI) process is performed with antimony (Sb) or germanium (Ge) to damage a silicon lattice of the substrate 100, forming amorphized regions 112
Implementation Method 2
a first rapid thermal annealing (RTA) process is performed to activate the first dopant and the co-implant dopant, regrow the amorphized regions to a substantially crystalline form
Implementation Method 3
performing a co-implantation process to implant a co-implant dopant into the amorphized regions, performing a first ion implantation process to implant a first dopant into the amorphized regions
Data Source
AI summary
A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.