MOS Transistor Termination Region Lateral Conductor Layout
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Solution Overview
Problem
The semiconductor industry faces challenges in reliably manufacturing metal oxide semiconductor (MOS) transistors with high stack height, leading to increased manufacturing costs and difficulties in forming gate and shield conductors with low resistance.
Innovation Solution
A method for forming MOS transistors with a configuration that includes active trenches with electrically isolated gate and shield conductors, where the conductors are formed to be substantially planar in the termination region, reducing step height and manufacturing costs, and utilizing a process that includes epitaxial layers, trench formation, and planarization techniques to improve process control and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two conductor stack configuration is used in the termination area, then electrical contact to gate and shield electrodes is achieved, but the stack height becomes high making manufacturing difficult and costly
Solution Approach 1:
The patent transitions from a vertical stacked configuration (one dimension) to a lateral adjacent configuration (another dimension). The gate conductor and shield conductor are positioned side-by-side in the termination region rather than stacked vertically, reducing stack height while maintaining electrical contact functionality through planarization techniques.
2Reliability
If a two conductor stack configuration is used in the termination area, then electrical contact to gate and shield electrodes is achieved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from a vertical stacked configuration (one dimension) to a lateral adjacent configuration (another dimension). The gate conductor and shield conductor are positioned side-by-side in the termination region rather than stacked vertically, reducing stack height while maintaining electrical contact functionality through planarization techniques.
3Manufacturing precision
If conventional trench formation is used, then gate and shield conductors are formed, but resistance remains high
Solution Approach 1:
The patent merges the gate conductor and shield conductor into a single continuous conductor structure that extends through the trench and into the termination region. This combined structure reduces resistance by providing continuous electrical pathways while maintaining the functional separation between gate and shield functions through appropriate positioning and insulation.
Data Source
AI summary
In one embodiment, a method of forming an MOS transistor includes forming the MOS transistor to have an active region and a termination region. Within the termination region the method includes forming a plurality of trenches having a conductor within the plurality of trenches. The method also includes forming another conductor to make electrical contact to one of the conductors within the plurality of trenches.