MOS Transistor with Multi-Via Source Drain Current Distribution
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Solution Overview
Problem
Existing high current transistor devices experience uneven current distribution and 'hot spots' due to single via stripes connecting source and drain, leading to electromigration issues and poor electrical performance.
Innovation Solution
Implementing multiple via stripes for source/drain connections, evenly distributed across transistor fingers, using a four-metal CMOS process to ensure all nodes (bulk, gate, drain, source) are accessible from all four edges, allowing for improved current distribution and automatic connections by abutting edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single via stripes are used to connect source and drain, then device complexity is reduced, but current distribution becomes uneven causing hot spots and electromigration issues
Solution Approach 1:
The single via stripe connection is segmented into multiple via stripes distributed across the transistor fingers. This segmentation divides the current path into multiple parallel routes, preventing current concentration in a single location and eliminating hot spots while maintaining structural manageability through systematic distribution.
Solution Approach 2:
Different regions of the transistor are provided with localized via stripe connections tailored to their specific current distribution needs. The via stripes are strategically positioned at different locations across the transistor fingers to ensure uniform current density throughout the device, with each local region receiving appropriate connection density.
2Reliability
If multiple via stripes are implemented for source/drain connections, then current distribution uniformity is improved, but manufacturing complexity increases
Solution Approach 1:
Multiple via stripes are merged into a unified metal layer structure that can be fabricated in a single processing step. The via stripes are formed as part of the standard CMOS metal layers (Metal3 and/or Metal4), combining multiple connection functions into the existing manufacturing workflow without requiring additional fabrication steps.
Solution Approach 2:
The metal layers serving as via stripes perform multiple functions: they provide source/drain connections, distribute current uniformly across transistor fingers, and serve as interconnect layers for other device connections. This multi-functionality reduces the need for dedicated structures and simplifies manufacturing by utilizing existing process capabilities.
3Power
If transistors are arranged in arrays for high current devices, then power output is increased, but current distribution across the array becomes non-uniform
Solution Approach 1:
The via stripe connections are arranged in a two-dimensional distributed pattern across the transistor array rather than linear connections. Multiple via stripes are positioned at different locations (e.g., left, center, right positions) across the array, creating a spatial distribution network that balances current flow across all transistor fingers simultaneously, enabling scalable array configurations.
Data Source
AI summary
A transistor device structured such that the bulk, gate, drain, and source are all accessible from all four edges of the device and such that current distribution is uniform over the device is provided. The transistor is created with a four-metal CMOS process. A bulk connection can be made with Metal 1, which is all around the device. A gate connection can be made with Metal 2, which is all around the device. Additionally, a drain/source connection can be made with Metal 3, which is all around the device. A source/drain connection can be made with Metal 4, which is all around the device. Source/drain connections are made with two or more evenly distributed via stripes to connect the source/drain parts of the transistor fingers. The transistor structure may be used to create an array of transistors for a high power output stage, with the transistors arranged in a checkerboard pattern. The connections of each transistor are automatic by abutting edges of the transistors.