MOS Transistor Impurity Gradients for Noise Reduction
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Solution Overview
Problem
Photoelectric conversion devices face challenges in reducing noise from hot carriers in MOS transistors, which degrades transistor reliability and increases dark current due to the miniaturization of MOS transistors and the damage caused by etching in the photoelectric conversion region.
Innovation Solution
A photoelectric conversion device with a distinct impurity concentration in the drains of MOS transistors between the photoelectric conversion region and the peripheral circuit region, allowing for optimized electric field relaxation and reduced noise, where the photoelectric conversion region has a lower impurity concentration to minimize hot carrier generation and the peripheral circuit region has a higher concentration for improved driving ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the MOS transistor is miniaturized to increase pixel density, then the pixel density increases, but the reliability of transistor properties degrades due to hot carrier generation
Solution Approach 1:
The patent applies different impurity concentrations to different regions: the photoelectric conversion region uses a lower impurity concentration (1×10^19 to 1×10^20 atoms/cm³) to reduce hot carrier generation and improve reliability, while the peripheral circuit region uses a higher impurity concentration (1×10^20 to 1×10^21 atoms/cm³) to maintain driving ability. This local differentiation resolves the contradiction between miniaturization and reliability.
Solution Approach 2:
The patent changes the impurity concentration parameter selectively in different regions. By controlling the impurity concentration in the drain region of MOS transistors in the photoelectric conversion region to be lower than in peripheral circuit regions, the patent reduces hot carrier effects while maintaining overall device functionality, thus improving reliability without sacrificing pixel density.
2Reliability
If the gate length is increased to ensure transistor reliability, then the reliability improves, but the miniaturization is hindered
Solution Approach 1:
The patent differentiates the drain region impurity concentration between photoelectric conversion region MOS transistors and peripheral circuit MOS transistors. This local quality differentiation allows the photoelectric conversion region to use lower impurity concentration for reliability while the peripheral region uses higher concentration for driving ability, resolving the contradiction without increasing gate length.
3Ease of manufacture
If the same impurity concentration is used in all MOS transistor drains, then the manufacturing process is simplified, but the hot carrier noise cannot be effectively reduced in the photoelectric conversion region
Solution Approach 1:
The patent implements local quality differentiation by setting the impurity concentration in the drain region of MOS transistors in the photoelectric conversion region to be lower (1×10^19 to 1×10^20 atoms/cm³) than in peripheral circuit regions (1×10^20 to 1×10^21 atoms/cm³). This selective differentiation effectively reduces hot carrier noise in the photoelectric conversion region while maintaining manufacturing feasibility through controlled ion implantation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces hot carrier-induced noise and degradation in the photoelectric conversion region while maintaining high driving ability in the peripheral circuit region, enhancing the reliability and sensitivity of the device without increasing production steps.
Implementation Method 1
a photoelectric conversion region (101) having a plurality of photoelectric conversion elements
Data Source
AI summary
A photoelectric conversion device includes a photoelectric conversion region having a plurality of photoelectric conversion elements and a first MOS transistor configured to read a signal in response to an electric charge of each photoelectric conversion element; and a peripheral circuit region having a second MOS transistor configured to drive the first MOS transistor and/or amplify the signal read from the photoelectric conversion region, the photoelectric conversion region and the peripheral circuit region being located on the same semiconductor substrate, wherein an impurity concentration in a drain of the first MOS transistor is lower than an impurity concentration in a drain of the second MOS transistor.