MOS Transistor Fabrication with Offset Sidewall Spacers
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Solution Overview
Problem
Existing MOS transistor fabrication processes result in relatively large parasitic resistance, affecting the performance of the transistors due to high surface and contact resistance in the gate and source/drain regions.
Innovation Solution
A method involving the formation of a gate structure on a semiconductor substrate with offset and main sidewall spacers, followed by the creation of lightly and heavily doped regions, and subsequent metal silicide regions to reduce parasitic resistance, using a self-alignment technique for metal silicide layer formation on the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication process is used, then manufacturing simplicity is maintained, but parasitic resistance becomes large
Solution Approach 1:
The fabrication process is segmented into multiple sequential stages: forming offset sidewall spacers, creating lightly doped regions, forming main sidewall spacers, and creating heavily doped regions. Each stage uses the previously formed structures as self-alignment masks, dividing the complex task of reducing parasitic resistance into manageable steps that collectively achieve the goal while maintaining process control
Solution Approach 2:
Offset sidewall spacers are formed in advance before the main sidewall spacers and doped regions. This preliminary structuring creates a self-alignment framework that guides subsequent processing steps, ensuring precise positioning of lightly and heavily doped regions without requiring additional alignment operations, thus reducing parasitic resistance through better geometric control
2Reliability
If metal silicide regions are formed to reduce parasitic resistance, then electrical conductivity is improved, but manufacturing complexity increases
Solution Approach 1:
The offset sidewall spacers and main sidewall spacers serve as self-alignment masks for the metal silicide formation process. The spacers automatically define the precise locations where metal silicide regions should be formed on the lightly and heavily doped regions, eliminating the need for separate photolithography alignment steps and reducing manufacturing complexity while ensuring optimal electrical contact
Solution Approach 2:
The patent employs sequential ion implantation with varying doping concentrations and depths to create distinct lightly and heavily doped regions. By controlling doping parameters (concentration, depth, distribution) and subsequently forming metal silicide regions on these differently doped areas, the process optimizes electrical conductivity through parameter optimization rather than adding complex structural elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces source/drain parasitic resistance from approximately 200 Ω/sq to 20 Ω/sq, enhancing the overall performance of the MOS transistor by optimizing the formation of metal silicide regions and controlling the depth and area of doped regions.
Implementation Method 1
a first metal silicide region 114 is formed on a surface of the source/drain regions by a metal-silicide process
Implementation Method 2
lightly doped regions 105 are formed in the semiconductor substrate 100 at both sides of the gate structure by a lightly doped ion implantation process
Data Source
AI summary
A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.