MOS Transistor Termination Region Planar Conductor Configuration
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Solution Overview
Problem
The semiconductor industry faces challenges in reliably manufacturing metal oxide semiconductor (MOS) transistors with high stack height, leading to increased manufacturing costs and difficulties in process control due to the complex structure of gate and shield conductors in the termination region.
Innovation Solution
A method for forming MOS transistors with a configuration that includes active trenches with electrically isolated gate and shield conductors, where the conductors are formed to be substantially planar in the termination region, reducing step height and manufacturing costs, and utilizing a process that includes epitaxial layers, trench formation, and planarization techniques to improve manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two different conductors are formed overlying each other as a two conductor stack in the termination region, then electrical contact to gate and shield electrodes is achieved, but the stack height becomes high making manufacturing difficult and costly
Solution Approach 1:
The patent transitions from a vertical stacked configuration (one dimension) to a lateral adjacent configuration (another dimension). The gate conductor and shield conductor are formed side-by-side in the termination region rather than one over the other, reducing stack height while maintaining electrical contact functionality through planar geometry
Solution Approach 2:
Instead of forming conductors vertically (bottom to top), the patent inverts the approach by forming them laterally (side by side). This inversion of the spatial arrangement resolves the manufacturing difficulty caused by high stack height while preserving the electrical contact function
2Reliability
If two different conductors are formed overlying each other as a two conductor stack, then electrical contact to gate and shield electrodes is achieved, but manufacturing cost increases
Solution Approach 1:
The patent reduces manufacturing cost by changing from vertical stacking to lateral adjacent formation of conductors. This dimensional change simplifies the fabrication process, reduces the number of deposition and etching steps required, and enables more efficient use of semiconductor wafer real estate, all of which contribute to lower manufacturing costs
3Device complexity
If conventional trench formation methods are used, then gate and shield regions are formed, but process control becomes difficult and manufacturing reliability decreases
Solution Approach 1:
The patent segments the conductor formation process into distinct lateral regions rather than attempting to form complex vertical stacks. The gate conductor and shield conductor are formed as separate lateral structures in the termination region, which simplifies process control and improves manufacturing precision by avoiding the difficulties of high-aspect-ratio vertical fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances process control, reduces manufacturing costs, and lowers the resistance of gate and shield conductors, improving the reliability and efficiency of transistor production.
Implementation Method 1
A method for forming MOS transistors with a configuration that includes active trenches with electrically isolated gate and shield conductors, where the conductors are formed to be substantially planar in the termination region, reducing step height and manufacturing costs, and utilizing a process that includes epitaxial layers, trench formation, and planarization techniques to improve manufacturability
Data Source
AI summary
In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.