MOS Transistor Row Decoder for Flash Memory Area Reduction
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Solution Overview
Problem
Conventional row decoders in flash memory devices are large in size, hindering the reduction in size of flash memory devices, particularly due to the need for multiple MOS transistors and complex level shifters for voltage transfer during operations like erase and read.
Innovation Solution
The semiconductor memory device incorporates a reduced row decoder configuration using two MOS transistors for the local row decoder and simplified level shifters, sharing global word lines and decode circuits to reduce the number of transistors and interconnects, allowing for a more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row decoder configuration is used, then voltage transfer during erase and read operations is achieved, but the row decoder size becomes large
Solution Approach 1:
The patent merges the functions of multiple MOS transistors into a simplified two-transistor configuration. The first MOS transistor handles voltage transfer for unselected word lines, while the second MOS transistor handles voltage transfer for the selected word line, combining multiple voltage transfer functions into a compact structure that reduces row decoder area while maintaining operational reliability
Solution Approach 2:
The MOS transistors in the patent are designed with independent back gate bias control, enabling them to perform multiple functions: transferring voltages during erase operations, transferring voltages during read operations, and providing voltage stress control. This multi-functionality eliminates the need for separate dedicated transistors for each operation, reducing overall row decoder size
2Reliability
If multiple MOS transistors are used for voltage transfer, then operational reliability is maintained, but device complexity increases
Solution Approach 1:
The patent combines multiple voltage transfer functions into just two MOS transistors with independent back gate control. This merging reduces the transistor count from multiple transistors to only two, significantly simplifying the device structure and reducing interconnect complexity while maintaining the ability to perform erase and read operations reliably
Solution Approach 2:
The patent introduces independent back gate bias as a control parameter for the MOS transistors. By controlling the back gate voltage independently of the source voltage, the transistors can dynamically adjust their threshold voltage and conductance, enabling reliable voltage transfer for different operations (erase and read) without requiring additional transistors, thus reducing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the size of the row decoder, improves reliability by minimizing voltage stress on memory cells, and enables a more compact flash memory design without compromising operational efficiency.
Implementation Method 1
first MOS transistors each provided for a corresponding one of the word lines and which transfer a first voltage to the word line unselected by the row decoder
Implementation Method 2
second MOS transistors each provided for a corresponding one of the word lines and which transfer a second voltage to the word line selected by the row decoder
Data Source
AI summary
A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, and first and second MOS transistors. The memory cell has a floating gate and a control gate. The word line connects commonly the control gates. The row decoder decodes a row address signal. The first MOS transistor transfers a first voltage to the word line unselected by the row decoder. The first MOS transistor has a drain connected to the word line and a source to which the first voltage is applied. A back gate bias for the first MOS transistor is controlled independently of a potential at the source of the first MOS transistor. The second MOS transistor transfers a second voltage to the word line selected by the row decoder. The second MOS transistor has a drain connected to the word line and a source to which the second potential is applied.