MOS Transistor Seam Sealing via Dielectric Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current MOS transistor manufacturing using selective epitaxial growth (SEG) technology faces issues with current leakage due to seams formed between epitaxial silicon layers and shallow trench isolations (STIs), which deepen and enlarge, causing excessive consumption of silicon atoms during the salicide process.
Innovation Solution
A method involving a deposition process to fill the seams between epitaxial silicon layers and STIs with a dielectric layer, followed by a second etching process to remove excess dielectric material, preventing seam enlargement and excessive silicon consumption during subsequent etching or cleaning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SEG process is performed to form epitaxial silicon layer in recesses, then good short channel character and low parasitical resistance are achieved, but seams are formed between epitaxial silicon layer and STI causing current leakage
Solution Approach 1:
A dielectric layer is introduced as an intermediary material between the epitaxial silicon layer and the STI structure. This dielectric layer fills the seam region and prevents direct contact that would cause current leakage, while not interfering with the electrical function of the transistor.
Solution Approach 2:
The seam filling process is performed preliminarily before the salicide process. By filling the seams with dielectric material in advance, the subsequent salicide process does not cause excessive silicon consumption or form salicide layers under the STI that would create current leakage paths.
2Manufacturing precision
If cleaning processes are performed to remove impurities after forming epitaxial silicon layer, then substrate cleanliness is improved, but seams grow larger and deeper exposing the substrate
Solution Approach 1:
The dielectric layer is deposited preliminarily to fill the seams before subsequent cleaning and etching processes. This preliminary filling prevents the seams from enlarging and deepening during later processing steps, while still allowing necessary cleaning to occur.
Solution Approach 2:
The dielectric layer serves as a cushioning material that protects the substrate from excessive exposure through the seams during subsequent processing. It provides a buffer that prevents the seams from growing larger and deeper while allowing the epitaxial silicon layer to be properly cleaned.
3Ease of manufacture
If salicide process is performed on substrate with existing seams, then source/drain contact is formed, but silicon atoms are excessively consumed and salicide layer forms under STI causing current leakage
Solution Approach 1:
The dielectric layer is deposited preliminarily to fill the seams before the salicide process. This prevents excessive silicon consumption during salicide formation by blocking the metal layer from reacting with silicon at the seam locations, and prevents salicide layer formation under the STI.
Solution Approach 2:
The dielectric layer acts as an intermediary barrier between the metal layer and the silicon substrate at the seam regions. This prevents direct reaction between the metal and silicon that would cause excessive silicon consumption and unwanted salicide formation under the STI.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents current leakage by sealing the seams with a dielectric layer, reducing damage to the substrate and epitaxial silicon layers during salicide formation, thereby enhancing the reliability of MOS transistors.
Implementation Method 1
performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively
Implementation Method 2
forming a dielectric layer in the seam
Data Source
AI summary
A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, accordingly a seam is formed in between the epitaxial silicon layer and the STI, forming a dielectric layer in the seam, and performing a self-aligned silicide (salicide) process.