High-Speed High-Power MOS Transistor With Segmented Drain
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high breakdown voltage and high operating speed simultaneously, particularly in RF power amplifiers, due to conflicting requirements that limit their efficiency and compatibility with standard CMOS processes.
Innovation Solution
The design incorporates an extended drain and additional field gates next to the active gate, along with shallow trench isolation strips, to create a high-speed high-power MOS transistor that operates with low on-resistance and high breakdown voltage, compatible with standard CMOS processes, and can be fabricated using both silicon-on-insulator and bulk CMOS technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate length is reduced to increase transistor speed, then the operating frequency is improved, but the breakdown voltage decreases
Solution Approach 1:
The drain region is segmented into multiple regions with different doping concentrations (first drain region with higher doping, second drain region with lower doping). This segmentation allows the device to achieve high speed through the lightly-doped second drain region while maintaining high breakdown voltage through the heavily-doped first drain region near the gate.
Solution Approach 2:
Different regions of the drain are given different local qualities through varying doping concentrations. The first drain region has high doping for voltage handling, while the second drain region has low doping for high-speed operation. This local quality differentiation resolves the contradiction between speed and breakdown voltage.
2Power
If transistors are stacked in cascode configuration to achieve high output power, then the voltage swing handling is improved, but the efficiency degrades and circuit design becomes challenging
Solution Approach 1:
The single transistor's drain is segmented into multiple regions that collectively handle the voltage swing, eliminating the need for cascode stacking. The first drain region handles high voltage while the second drain region enables high-speed operation, allowing one transistor to perform what previously required multiple stacked transistors.
Solution Approach 2:
The single transistor with segmented drain structure performs multiple functions simultaneously: it provides high voltage handling capability, high-speed operation, and high output power in one device, replacing the need for complex cascode configurations of multiple transistors.
3Speed
If a complicated device architecture is used to achieve high speed and high output power, then the performance is improved, but the fabrication complexity increases and compatibility with standard CMOS process is reduced
Solution Approach 1:
The invention achieves high-speed high-power performance by changing the doping concentration parameter in different drain regions rather than by complicating the device architecture. This parameter-based approach maintains compatibility with standard CMOS fabrication processes while achieving the desired performance.
Solution Approach 2:
Instead of achieving high power through architectural complexity (stacking transistors), the invention inverts the approach by using parameter variation (doping concentration) within a simple single-transistor structure. This simplifies the device architecture while maintaining high performance.
Data Source
AI summary
High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.