Self-Aligned MOS Transistor Contacts via Gate Silicide Oxidation
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Solution Overview
Problem
The challenge lies in forming gate, source, and drain contacts on MOS transistors with nanometric dimensions, where misalignment risks generating short-circuits between the source and drain regions and the gates, particularly for gate lengths smaller than 20 nm, due to difficulties in accurately aligning masks during the contact formation process.
Innovation Solution
A method involving the steps of covering the structure with a second insulating material, oxidizing the gate silicide to bury it under silicon oxide, selectively removing the insulating material, and then applying a conductive material, which allows for self-aligned contact formation without a critical mask alignment, thereby avoiding short-circuits. This method includes using silicon oxide for the insulating materials and tungsten or similar conductive materials, with thermal oxidation at temperatures below 700°C to maintain sufficient gate silicide thickness and reduce stray capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If mask alignment is used to form contacts on nanometric MOS transistors, then contact formation is achieved, but misalignment risks generating short-circuits between source/drain regions and gates
Solution Approach 1:
The gate is oxidized beforehand to create a protruding oxide structure that serves as a self-aligned stop marker for subsequent etching operations. This preliminary oxidation action ensures that the contact openings will automatically stop at the correct position, eliminating alignment errors that would occur with conventional mask-based methods.
Solution Approach 2:
The gate oxide structure serves itself as the alignment reference for contact formation. The protruding oxide naturally defines the etch stop position, making the system self-aligning without requiring external mask alignment. The structure's own geometry provides the positioning information needed for precise contact formation.
2Productivity
If gate length is decreased to nanometric dimensions, then transistor density is improved, but mask alignment becomes increasingly difficult and short-circuit risk increases
Solution Approach 1:
The solution moves the alignment reference from the lateral plane (mask patterns) to the vertical dimension (protruding gate oxide). By creating a height difference that protrudes from the gate surface, the alignment reference becomes three-dimensional, allowing etching to self-align based on the vertical profile rather than relying on two-dimensional mask precision.
Solution Approach 2:
The method changes the physical state and geometry of the gate structure by oxidizing it to create a protruding oxide layer. This parameter change in the gate's surface topology transforms it from a flat structure requiring external alignment to a self-aligned structure where the oxide protrusion itself defines the contact position.
3Reliability
If thermal oxidation is performed at high temperature, then gate oxide formation is complete, but gate silicide thickness may be reduced excessively
Solution Approach 1:
The oxidation process is controlled to perform partial action - enough to create the necessary protruding oxide structure for self-alignment, but not so much as to completely consume the gate silicide. The oxidation is stopped at the point where the protrusion is sufficient for alignment purposes while maintaining adequate silicide thickness for electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned gate, source, and drain contacts on MOS transistors with very small gate lengths, reducing the risk of short-circuits and allowing for precise control of contact formation, even with minimal gate silicide thickness, thus ensuring reliable contact formation without requiring critical mask alignment.
Implementation Method 1
oxidizing the gate so that the gate silicide buries and covers with a silicon oxide
Data Source
AI summary
A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.