MOS Transistor Layout With Shorter Gate and Drain Wiring
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Solution Overview
Problem
In conventional MOS transistors used in high-frequency analog signal amplifier circuits, the drain region's ring-shaped configuration requires multi-layer wiring, leading to longer wiring lengths and increased losses, especially in millimeter-wave-band circuits.
Innovation Solution
The semiconductor device design includes MOS transistors with source regions having ends narrower than the central part, allowing for shorter gate and drain wire lengths by diagonal wiring at 45 degrees, which reduces wiring resistance and losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drain region is configured in a ring shape surrounded by the gate electrode, then the transistor structure is well-defined, but multi-layer wiring via contacts is required which increases wiring length
Solution Approach 1:
The invention transitions from a planar ring-shaped drain region requiring multi-layer wiring to a three-dimensional FinFET structure where the drain is formed as a fin extending vertically from the substrate. This dimensional change allows the drain to be accessed laterally at the same level as the source, eliminating the need for vertical vias and reducing wiring length while maintaining proper transistor structure definition through the fin geometry and gate wrapping.
2Reliability
If gate wiring and drain wiring become long, then connectivity is achieved, but circuit losses increase in millimeter-wave-band signals
Solution Approach 1:
By forming the drain as a vertical fin structure rather than a planar region, the invention enables lateral access to the drain at the surface level, significantly shortening the drain wiring path. This dimensional transformation reduces both the physical length of interconnects and the number of via transitions, thereby minimizing signal losses in high-frequency millimeter-wave applications while preserving proper electrical connectivity.
Solution Approach 2:
The invention changes the geometric parameters of the drain region from a two-dimensional planar shape to a three-dimensional fin structure with controlled height and width. This parameter transformation allows optimization of the drain wiring path length and reduces the number of interconnect layers required, directly addressing signal integrity and loss concerns in millimeter-wave circuits.
Data Source
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AI summary
The wiring length of MOS transistors is shortened. A source region has both ends made smaller in width than a central part. A first channel region and a second channel region are placed adjacent to the corresponding outer peripheral parts divided by the both ends. A first drain region and a second drain region are placed adjacent to the first channel region and the second channel region, respectively. Gate electrodes are placed on respective surfaces of the first channel region and the second channel region through an insulating film and joined to each other near a first end of the source region and connected to a gate wire. Drain electrodes are placed on the respective surfaces of the first drain region and the second drain region and joined to each other near a second end and connected to a drain wire. At least one of the gate wire or the drain wire is made smaller in width than the central part of the source region.