MOS Transistor Side Wall Structure for Parasitic Memory Suppression
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Solution Overview
Problem
In semiconductor devices, process charging during production can lead to trapped electric charges in silicon nitride films, affecting the threshold voltage of memory transistors and causing characteristic variations in MOS transistors due to parasitic memory cells formed on their side walls.
Innovation Solution
A semiconductor device configuration and production method that includes a memory transistor with an ONO structure and a MOS transistor with a specific side wall structure, where the second silicon nitride film diffuses electric charges into the substrate, and the MOS transistor's side wall is designed to prevent parasitic memory cell formation, using additional silicon oxide and nitride films to manage charge accumulation and diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electric charges are accumulated in the silicon nitride film during the production process, then the threshold voltage of the memory transistor changes and data can be stored, but the threshold voltage varies due to process charging
Solution Approach 1:
The patent divides the semiconductor substrate into two distinct regions: a first region containing the memory transistor with ONO structure for data storage, and a second region containing the MOS transistor without silicon nitride film for stable electrical characteristics. This spatial segmentation allows each transistor type to have optimized structures for their specific functions, resolving the contradiction between data storage capability and threshold voltage consistency.
Solution Approach 2:
The patent applies different structural configurations to different locations on the substrate. The memory transistor region receives the full ONO structure with silicon nitride film for charge accumulation, while the MOS transistor region deliberately excludes the silicon nitride film to prevent parasitic memory cell formation. This local quality differentiation ensures each region has the properties needed for its specific function.
2Ease of manufacture
If a silicon nitride film is formed on the side wall of the MOS transistor, then the structure is complete, but parasitic memory cells are formed causing characteristic variations
Solution Approach 1:
The patent applies the silicon nitride film selectively only where needed for memory function (in the first region for memory transistors) and deliberately omits it where it would cause harm (in the second region for MOS transistors). This localized application strategy maintains manufacturing simplicity while preventing parasitic memory cell formation and ensuring electrical characteristic stability.
Solution Approach 2:
The patent recognizes that the silicon nitride film causes parasitic memory cell formation on MOS transistor side walls, and converts this potential harm into a benefit by using the same fabrication process to selectively form the film only in regions where charge accumulation is desired (memory transistors), while intentionally excluding it from regions where it would be harmful (MOS transistors).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the influence of process charging on the threshold voltage of memory transistors and suppresses characteristic variations in MOS transistors, optimizing the operation of both types of transistors without requiring additional photolithography steps in the production process.
Implementation Method 1
excess electric charges (process charging) trapped in the first silicon nitride film 21 during the production process can be diffused into the silicon substrate 12 via the second silicon nitride film 23
Data Source
AI summary
A semiconductor device includes: a memory transistor including a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a first gate electrode that are disposed in sequence on a substrate; and a MOS transistor including a third silicon oxide film and a second gate electrode that are disposed in sequence on the substrate. The memory transistor has a side wall including an extending portion of the first silicon oxide film, a second silicon nitride film that is in contact with the first silicon nitride film, and a fourth silicon oxide film that are disposed in sequence on the substrate, and the MOS transistor has a side wall including a fifth silicon oxide film that is disposed on the substrate.