MOS Transistor SiGe Source/Drain Density Uniformity
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Solution Overview
Problem
The existing embedded SiGe technology for PMOS transistors results in non-uniform SiGe source/drain regions due to varying transistor densities across different regions of a semiconductor substrate, leading to uneven ion distribution, higher resistance, and leakage currents, which affects the yield and performance of PMOS transistors.
Innovation Solution
The method involves forming dummy SiGe growth regions in areas with lower transistor densities to increase the total density of SiGe growth regions, ensuring uniform epitaxial growth and deposition rates across all regions, thereby matching the density and height of SiGe source/drain regions in regions with higher transistor densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded SiGe technology is used to increase carrier mobility in PMOS transistors, then the performance of PMOS transistors is improved, but the uniformity of SiGe source/drain regions deteriorates due to varying transistor densities across different regions
Solution Approach 1:
The patent applies local quality by introducing dummy SiGe growth regions specifically in low-density areas (such as peripheral regions) to create a non-uniform distribution pattern that achieves uniform reaction gas consumption. The dummy regions are selectively placed based on the local transistor density, allowing different regions to have different structures that collectively achieve uniformity in the epitaxial growth process
Solution Approach 2:
The patent changes the parameter of SiGe growth region density by adding dummy regions in low-density areas. This modifies the reaction gas consumption distribution across the substrate, transforming the non-uniform consumption pattern into a uniform one, thereby ensuring uniform epitaxial growth rates and consistent SiGe source/drain region heights across all regions
2Speed
If epitaxial growth process is used to form SiGe in trenches, then the carrier mobility is increased, but the height of formed SiGe structures becomes non-uniform due to different reaction gas consumption rates in different regions
Solution Approach 1:
The patent introduces dummy SiGe growth regions in specific low-density areas to create local modifications in the reaction gas consumption pattern. These dummy regions are strategically placed to compensate for the lower gas consumption in peripheral areas, ensuring that the overall reaction gas distribution becomes uniform across the entire substrate, thereby achieving uniform SiGe growth heights
Solution Approach 2:
The patent achieves equipotentiality in terms of reaction gas consumption by adding dummy regions that balance the gas consumption between high-density and low-density regions. This creates an equivalent consumption level across all regions, ensuring that the epitaxial growth process produces uniform SiGe source/drain regions with consistent heights and properties
3Ease of manufacture
If ion implantation is performed on non-uniform embedded source/drain regions, then the manufacturing process is completed, but the ion distribution becomes uneven leading to higher resistance and leakage currents
Solution Approach 1:
The patent modifies the physical parameter of SiGe growth region distribution by adding dummy regions, which changes the consumption pattern of reaction gas during epitaxial growth. This parameter change ensures uniform growth rates and consistent SiGe region heights, which in turn ensures uniform ion implantation depth and distribution, reducing leakage currents and improving device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of SiGe source/drain regions, improves the yield and performance of PMOS transistors by ensuring consistent ion distribution and reduced leakage currents, and maintains the stress environment for PMOS transistors.
Implementation Method 1
The crystal lattice mismatch between SiGe and the silicon substrate may generate the compressive stress to the channel region
Implementation Method 2
The process for forming SiGe in the trenches may be an epitaxial growth process
Data Source
AI summary
A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second region; and forming first transistors on the semiconductor substrate. Wherein source/drain regions of the first transistors are configured as SiGe growth regions; and a first density of SiGe growth regions in the first region is smaller than a second density of SiGe growth regions in the second region. The method also includes forming dummy SiGe growth regions in the first region to increase the first density such that the total density of SiGe growth regions in the first region is in a range similar to the second density; and forming trenches in the first region and the second region and the dummy SiGe growth region. Further, the method includes forming embedded source/drain regions of the first transistors and dummy SiGe regions.