MOS Transistor Source/Drain Extension Formation via Epitaxial Growth
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Solution Overview
Problem
The existing methods for manufacturing metal oxide semiconductor transistors damage the source/drain extension areas due to high temperature processes, leading to leakage issues and ineffective ultra shallow junctions, as the metal silicide contacts the silicon substrate, disrupting the original crystal lattice.
Innovation Solution
The method involves forming epitaxial layers outside disposable spacers around the gate, allowing for the creation of source/drain extension areas after the selective epitaxial growth process, thus avoiding direct contact with the silicon substrate and maintaining the integrity of these areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth process is used to raise source/drain height, then silicide and silicon substrate don't contact directly, but the high temperature (690-790°C) damages the source/drain extension areas
Solution Approach 1:
The source/drain extension areas are formed before the selective epitaxial growth process. By performing the ion implantation to create LDD regions prior to the high-temperature SEG process, the extension areas are already in place and can be protected by the subsequently grown epitaxial layers, preventing both silicide-substrate contact and temperature-induced damage
Solution Approach 2:
The source/drain structure is segmented into multiple components: source/drain extension areas (LDD), epitaxial layers, and main source/drain regions. This segmentation allows each component to be formed at appropriate temperatures and conditions, with the extension areas created first at lower temperatures, then protected by epitaxial growth at higher temperatures
2Reliability
If self-aligned silicide process is used, then Ohmic contact among gate and source/drain is improved, but metal expands into silicon substrate and damages the original crystal lattice
Solution Approach 1:
The source/drain extension areas are formed preliminarily before the silicide formation process. By creating the LDD regions first through ion implantation, the subsequent silicide deposition and formation occurs on already-established doped regions, ensuring proper electrical contact while maintaining lattice integrity through the buffer effect of the extension areas
3Manufacturing precision
If source/drain extension areas are formed before epitaxial layers, then ultra shallow junction is achieved, but high temperature process damages the extension areas
Solution Approach 1:
The source/drain extension areas are formed in advance through ion implantation before the selective epitaxial growth process. This preliminary formation establishes the ultra-shallow junction profile at the desired depth, and the subsequent epitaxial growth occurs in a controlled manner that preserves the pre-formed extension areas while building protective layers
Solution Approach 2:
The patent employs precise control of process parameters including ion implantation energy and dose to create the extension areas at specific depths, followed by controlled epitaxial growth conditions that minimize diffusion and maintain the shallow junction profile while providing thermal protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage from high temperature processes, enabling the formation of ultra shallow junctions with maintained source/drain extension areas and preventing silicide-substrate contact, thereby enhancing transistor efficacy.
Implementation Method 1
utilizing the selective epitaxial growth (SEG) process to stand the source/drain high
Data Source
AI summary
A method of manufacturing a metal oxide semiconductor is provided. The method includes forming an offset spacer and a disposable spacer around the offset spacer. Then, forming a plurality of epitaxial layers outside the disposable spacer and removing the disposable spacer. In addition, the method includes forming a plurality of source/drain extension areas in the substrate outside the offset spacer and the epitaxial layers. Because the source/drain extension areas are formed after the selective epitaxial growth process, the thermal of the selective epitaxial growth process does not damage the source/drain extension areas.