MOS Transistor Source/Well Heterojunction for Breakdown Voltage
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Solution Overview
Problem
Conventional MOS transistors, such as LDMOS transistors, face a challenge in achieving both increased breakdown voltage and reduced on-resistance, as increasing the drift region to enhance breakdown voltage often leads to increased on-resistance, making it difficult to balance these two desirable traits.
Innovation Solution
The method involves fabricating a MOS transistor with a source/well heterojunction by forming a lightly doped drift region and a source region with a different lattice structure, such as silicon germanium or silicon carbide, to create a higher barrier between the source and channel, thereby increasing breakdown voltage while reducing on-resistance through enhanced carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drift region between channel and drain is increased to achieve increased breakdown voltage, then breakdown voltage is improved, but on-resistance increases which is undesirable
Solution Approach 1:
The patent introduces a heterojunction layer with different material composition (e.g., SiGe or SiC) at the source-well interface, creating localized regions with different electrical properties. This allows the drift region to maintain its length for high breakdown voltage while the heterojunction provides enhanced carrier mobility and reduced on-resistance through its superior material properties
Solution Approach 2:
The patent employs composite material structure by combining different semiconductor materials (such as Si/SiGe or Si/SiC heterojunction) in the source-well region. This composite approach enables simultaneous achievement of high breakdown voltage (through appropriate drift region design) and low on-resistance (through the superior electrical properties of the heterojunction materials)
Data Source
AI summary
According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.