HV and LV MOS Transistor Spacer Optimization
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Solution Overview
Problem
Existing methods for manufacturing MOS transistors with epitaxial source and drain regions struggle to optimize spacer width for both high-voltage (HV) and low-voltage (LV) transistors, leading to performance degradation and increased risk of spacer breakdown when trying to accommodate varying voltage operations.
Innovation Solution
A method involving the sequential formation of gate stacks, selective deposition and etching of insulating spacers, and epitaxial growth of doped semiconductor materials, where HV transistors have wider spacers and thicker gate insulators compared to LV transistors, using materials like silicon nitride and silicon oxide, to maintain performance across voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of spacers is increased to decrease the risk of breakdown and stray capacitance in HV transistors, then reliability and capacitance performance improve, but the performance of LV transistors degrades
Solution Approach 1:
The device is segmented into two distinct transistor types (HV and LV) with different spacer configurations. HV transistors receive wider spacers made of first insulating material, while LV transistors receive narrower spacers made of second insulating material, allowing each type to be optimized independently for its specific voltage requirements
Solution Approach 2:
Different spacer widths and materials are applied locally to different transistor regions based on their specific voltage requirements. The first insulating material with wider spacers is used specifically for HV transistors, while the second insulating material with narrower spacers is used specifically for LV transistors, ensuring each region has the optimal spacer characteristics for its function
2Ease of manufacture
If a single spacer width is used for both HV and LV transistors, then manufacturing complexity is reduced, but either breakdown risk increases for HV or performance degrades for LV
Solution Approach 1:
The manufacturing process is segmented into separate spacer formation sequences for HV and LV transistors. First spacers are formed for HV transistors, then second spacers are formed for LV transistors, allowing independent optimization of each spacer's width and material properties without compromising the other transistor type
Solution Approach 2:
The method performs preliminary actions by first forming spacers for HV transistors, then subsequently forming spacers for LV transistors. This sequential approach allows each spacer formation step to be optimized independently, with the first spacer formation addressing HV requirements and the second spacer formation addressing LV requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous optimization of spacer width and epitaxial growth for both HV and LV transistors, reducing the risk of breakdown and maintaining performance across voltage ranges by using distinct spacer materials and epitaxial growth for each type of transistor.
Implementation Method 1
a gate insulator layer...arranged between the gate electrode and the semiconductor layer
Implementation Method 2
growing a first doped semiconductor material...from the exposed surface of the semiconductor layer
Data Source
AI summary
A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.