MOS Transistor Stress Bumps for Mobility Enhancement
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Solution Overview
Problem
In semiconductor devices, miniaturization leads to short-channel effects that reduce mobility and current-carrying ability, and uniform tensile or compression stresses applied to entire chips can degrade performance or reliability of certain circuit blocks or sections.
Innovation Solution
A semiconductor device with a single-crystal semiconductor layer and circuit blocks featuring bumps that apply specific stresses, such as compression and tensile stresses, to MOS transistors to enhance carrier mobility, using a protective film and strategically placing bumps to improve electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity density in substrate is increased to suppress short-channel effect, then drain-source leakage current is reduced, but mobility is reduced and drive current is reduced
Solution Approach 1:
The patent applies different impurity densities to different regions: high impurity density in the substrate to suppress short-channel effects and reduce leakage, while maintaining low impurity density in the channel layer to preserve high carrier mobility. This spatial differentiation of impurity concentration resolves the contradiction between reliability and speed.
2Speed
If uniform tensile or compression stresses are applied to entire chip, then carrier mobility is improved, but performance or reliability of certain circuit blocks is degraded
Solution Approach 1:
The patent applies stresses locally to specific circuit blocks or sections that require performance enhancement rather than uniformly across the entire chip. This selective local stress application improves carrier mobility in targeted areas while avoiding performance degradation in other circuit blocks, resolving the contradiction between speed and reliability.
3Productivity
If miniaturization is pursued to achieve higher performance, then packing density is increased, but short-channel effects increase and reduce mobility
Solution Approach 1:
The patent maintains low impurity density specifically in the channel layer region to preserve high carrier mobility despite miniaturization, while allowing higher impurity density in the substrate for short-channel effect suppression. This localized quality control enables continued miniaturization for higher packing density without sacrificing mobility in the critical channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases carrier mobility and improves the performance of semiconductor devices by applying targeted stresses to specific areas, allowing for higher speed and lower current consumption.
Implementation Method 1
the use of piezoelectric effect which produces mechanical strains in silicon devices is well known as a method for changing electrical conductivity by changing the mobility of the carriers moving in the channel layers
Data Source
AI summary
A semiconductor device 20 formed on a semiconductor chip substrate 30 has a plurality of circuit blocks made up of circuits each containing at least a metal oxide semiconductor (MOS) transistor 36, the circuit blocks being covered on top with a protective film 41 to protect the circuits. A plurality of bumps 23a, 23b, 23c are formed, at least via the protective film 41, only on circuit blocks whose current-carrying ability and threshold voltage do not satisfy predetermined values and which are in need of performance enhancement. The bumps 23a, 23b, 23c impose stresses on the MOS transistors 36, increasing the mobility of the MOS transistors 36 and thereby improving the performance of the semiconductor device 20.