Segmented Stress Layers for MOS Transistor NBTI Control
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Solution Overview
Problem
Conventional stress control methods for improving semiconductor device performance, such as using compressive stress layers on P-channel devices, often lead to negative bias temperature instability (NBTI) degradation, reducing current gain and affecting device reliability.
Innovation Solution
A method involving the formation of a tensile stress layer on specific MOS transistors and a compressive stress layer on others, with precise layer management to avoid NBTI degradation, using silicon nitride layers and PECVD techniques, while minimizing the number of photomasks to maintain cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a compressive stress layer is formed on the P-channel device to improve current gain, then the current gain and efficiency are improved, but the device reliability is degraded due to threshold voltage shift and NBTI
Solution Approach 1:
The stress layer is segmented into different types: a first stress layer (tensile) formed on the I/O P-channel MOS transistor to prevent NBTI degradation, and a second stress layer (compressive) formed on the core P-channel MOS transistor to improve current gain. This segmentation allows different stress conditions for different functional blocks, resolving the contradiction between reliability and performance.
Solution Approach 2:
Different stress characteristics are applied to different local regions: tensile stress is applied locally to the I/O transistor region to prevent threshold voltage shift, while compressive stress is applied locally to the core transistor region to enhance current gain. This local differentiation resolves the contradiction by optimizing each region for its specific function.
2Speed
If the component size is reduced to achieve high speed and low power consumption, then the device performance is improved, but the fabrication technique limitation and high cost prevent further reduction
Solution Approach 1:
Instead of further reducing component size, the invention changes the stress parameter (from uniform compressive to differentiated tensile/compressive) to improve device performance. This parameter change achieves high speed and low power consumption through stress engineering rather than size reduction, avoiding fabrication technique limitations and high costs.
3Ease of manufacture
If a single stress layer is used for all P-channel devices, then the manufacturing process is simplified, but the device performance is compromised due to NBTI in I/O transistors
Solution Approach 1:
The stress layer is segmented into a first stress layer (tensile) for I/O transistors and a second stress layer (compressive) for core transistors. This segmentation prevents NBTI degradation in I/O devices while maintaining good current gain in core devices, achieving excellent device performance without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents threshold voltage shift and NBTI degradation, enhancing device performance without increasing fabrication costs by ensuring H+ is not accumulated in the gate dielectric layer, even under negative bias conditions.
Implementation Method 1
using silicon nitride layers and PECVD techniques
Implementation Method 2
a method of using the stress control had been proposed to overcome the limitation of reducing the component size
Data Source
AI summary
A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.