Stressed Cap Layer for MOS Transistor Leakage Reduction
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Solution Overview
Problem
Existing semiconductor transistor devices require expensive methods to achieve improved functionality and performance, particularly in silicon nitride spacer-less semiconductor MOS/CMOS transistor devices.
Innovation Solution
A method involving the formation of a semiconductor substrate with a shallow trench isolation region, gate dielectric layer, gate electrode with vertical sidewalls, liner, ion implantation for source/drain regions, silicide layer formation, etching to create a step height, removal of silicon nitride spacers, and deposition of a stressed cap layer with specific stress status extending to the trench isolation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods with silicon nitride spacers are used, then device performance is maintained, but fabrication cost increases and manufacturing complexity increases
Solution Approach 1:
The invention removes the silicon nitride spacer component entirely from the device structure. The method forms source and drain regions directly adjacent to the gate electrode without requiring spacers, thereby eliminating the need for spacer deposition, patterning, and etching processes while maintaining acceptable device performance
Solution Approach 2:
Instead of using spacers to define source/drain regions indirectly, the invention inverts the approach by directly forming source/drain regions through ion implantation using the gate electrode itself as the mask, eliminating the intermediary spacer structure
2Manufacturing precision
If silicon nitride spacers are used, then source/drain region definition is achieved, but manufacturing complexity and fabrication cost increase
Solution Approach 1:
The invention extracts and removes the silicon nitride spacer from the fabrication process, achieving source/drain region definition through direct ion implantation using the gate electrode as a mask, thereby reducing the number of process steps and manufacturing complexity
Solution Approach 2:
The gate electrode serves multiple functions: it acts as both the control electrode and the implantation mask for defining source/drain regions, eliminating the need for separate spacer structures and simplifying the overall device architecture
3Reliability
If strained silicon layer is used, then carrier mobility increases, but manufacturing complexity increases
Solution Approach 1:
The invention changes the physical parameter of the silicon layer by introducing strain through SiGe source/drain regions. The strained silicon channel is formed by epitaxial growth with controlled strain parameters, optimizing carrier mobility while managing the complexity through parameter control rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the electrical performance of MOS/CMOS transistor devices by increasing saturation current and preventing contact junction leakage, while eliminating the need for silicon nitride spacers, thus reducing fabrication costs.
Implementation Method 1
a stressed cap layer is formed over the gate electrode and the source/drain regions. The stressed cap layer has a specific stress status that increases the saturation current of the MOS transistor device
Implementation Method 2
ion implanting the active area using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the active area
Implementation Method 3
performing an etching process to etch away a thickness of the STI region, thereby forming a step height h at interface between the active area and the STI region
Data Source
AI summary
A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.