High and Low Voltage MOS Transistor Integration on Common Substrate
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Solution Overview
Problem
The integration of low-voltage and high-voltage transistors in semiconductor devices poses challenges due to incompatibility, leading to separate integrated circuits, which complicates device fabrication and increases costs, especially with the need for additional structures like guard rings and triple wells to enhance electrical isolation.
Innovation Solution
A semiconductor device fabrication process that allows both high-voltage and low-voltage transistors to be formed on the same substrate using a reduced number of fabrication processes and masks, with specific dopant implantation depths and similar gate oxide thicknesses, eliminating the need for guard rings and triple wells in some applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate integrated circuits are used for low-voltage and high-voltage devices, then electrical compatibility is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent combines both low-voltage and high-voltage devices on a single integrated circuit substrate. By using a common substrate with shared fabrication processes for wells, isolation structures, and dopant implantation, the design eliminates the need for separate circuits while maintaining electrical compatibility through proper device design and isolation techniques.
Solution Approach 2:
The patent creates a universal substrate that can accommodate both low-voltage and high-voltage devices. The fabrication process is designed to be multi-functional, supporting the formation of different device types (NMOS, PMOS, high-voltage asymmetric devices) using the same sequence of steps, including well formation, isolation structure creation, and dopant implantation processes.
2Reliability
If guard rings and triple wells are added for electrical isolation, then electrical isolation between transistors is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the need for additional guard rings and triple well structures by incorporating electrical isolation functionality directly into the basic isolation structures and device design. The isolation is achieved through the fundamental fabrication process rather than requiring extra isolation components, thereby simplifying manufacturing.
Solution Approach 2:
The isolation structures and device design self-provide the necessary electrical isolation between transistors. The fabrication process inherently creates sufficient isolation through the formation of wells and isolation structures, eliminating the need for separate guard ring or triple well structures to provide this function.
3Adaptability or versatility
If multiple fabrication processes and masks are used for integration, then device functionality is improved, but productivity and manufacturing efficiency decrease
Solution Approach 1:
The patent merges the fabrication processes for low-voltage and high-voltage devices into a single integrated process sequence. By combining the formation of different device types into one unified fabrication flow using common masks and process steps, the design achieves full device functionality without requiring separate fabrication sequences, thereby maintaining high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and maintains effective electrical isolation between transistors, enabling efficient integration of both high-voltage and low-voltage devices on a common substrate without the complexity and expense of additional isolation structures.
Implementation Method 1
using a first implantation process to simultaneously implant a dopant of first conductivity type to a second depth in the substrate to form a channel region in the first low-voltage transistor well and a drain region in the first high-voltage transistor well
Data Source
AI summary
Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.