MOS Transistor Threshold Voltage Control for Parasitic Diode Current Suppression
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Solution Overview
Problem
The existing semiconductor memory devices experience parasitic diode current issues due to timing deviations during transitions between selected and non-selected states, which can lead to unwanted current flow through parasitic diodes in MOS transistors.
Innovation Solution
The implementation of MOS transistors with threshold voltages set based on the forward voltage of parasitic diodes to prevent parasitic diode current, using specific conditions for high and low voltage line non-selected transistors to ensure they are turned on before the parasitic diodes, thereby avoiding current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If MOS transistors are used as switches in word lines and bit lines to selectively apply voltage to memory cells, then write and read operations can be performed bit by bit, but parasitic diode current may flow in the substrate due to timing deviation during state transitions
Solution Approach 1:
The patent applies preliminary action by setting the threshold voltage of MOS transistors in advance based on the forward voltage characteristics of parasitic diodes. This pre-configured threshold voltage ensures that during timing deviations, the transistor channel remains conductive only when the parasitic diode is forward-biased, preventing harmful current flow before the actual switching event occurs
Solution Approach 2:
The patent changes the electrical parameter of the MOS transistor by optimizing its threshold voltage to a specific range (0.7V to 1.3V) that corresponds to the forward voltage of the parasitic diode. This parameter change transforms the transistor's switching behavior to inherently suppress parasitic current while maintaining normal memory cell selection functionality
2Reliability
If high breakdown voltage transistors are used to prevent parasitic diode current, then current flow can be suppressed, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of increasing breakdown voltage, the patent changes the threshold voltage parameter to a moderate range (0.7V to 1.3V) that provides parasitic current suppression through proper channel conduction control. This parameter optimization achieves reliability without requiring high breakdown voltage transistors, simplifying device design and manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses parasitic diode current regardless of timing deviations, allowing for reliable operation without the need for high breakdown voltage transistors, thus enhancing the memory device's performance and efficiency.
Implementation Method 1
a first condition in which a channel of the high voltage line non-selected transistor is conductive when a gate-to-source voltage of the high voltage line non-selected transistor exceeds a threshold voltage
Implementation Method 2
when a voltage higher than a forward voltage is applied to the parasitic diode of the MOS transistor due to a timing deviation during the transition between a selected state and a non-selected state of the memory cell, a parasitic diode current may flow in the substrate
Data Source
AI summary
A semiconductor memory device includes a first transistor connected between a high voltage line connected to a first end of a memory element and a first power supply terminal, and a second transistor connected between the high voltage line and a second power supply terminal, a third transistor connected between a low voltage line connected to a second end of the memory element and a third power supply terminal, and a fourth transistor connected between the low voltage line and a fourth power supply terminal. The second and fourth transistors satisfy the condition: |Vth|<|VG−VB|+VF, where Vth is a threshold voltage thereof, VG is a voltage difference between a gate and a source or drain thereof, VB is a bias voltage applied to a body thereof, and VF is a minimum voltage at which a parasitic diode current flows.