MOS Transistor Trench Gate for Voltage Threshold Control
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Solution Overview
Problem
Current metal-oxide semiconductor field-effect transistor (MOSFET) technologies face challenges in efficiently modulating conductivity and forming effective channel regions for high current applications and electrostatic discharge (ESD) clamping, particularly due to limitations in voltage threshold control and electrical isolation.
Innovation Solution
The development of MOS transistor structures featuring trench and liner isolation regions, where the trench region acts as a gate electrode and the liner forms a gate dielectric, allowing for the formation of channel regions responsive to applied voltages and enabling efficient current paths and ESD clamping through varying doping levels and materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOSFET structures are used, then manufacturing is simpler, but voltage threshold control and conductivity modulation are insufficient for high current applications
Solution Approach 1:
The device is segmented into distinct functional regions: a trench isolation region serving as gate electrode, a liner region as gate dielectric, and a semiconductor region with controlled doping profiles. This segmentation allows independent optimization of voltage threshold control through the trench/liner structure while maintaining manufacturability through standardized fabrication processes.
Solution Approach 2:
Different regions of the device are assigned different doping levels and material compositions to achieve local optimization. The semiconductor region has a first doping level, the liner has a second doping level, and the trench region has a third doping level, allowing precise control of voltage threshold and conductivity modulation in specific areas without affecting the entire device structure.
2Productivity
If higher doping levels are used to improve conductivity, then current handling capability increases, but voltage threshold control becomes more difficult
Solution Approach 1:
The patent employs a multi-level doping strategy where different regions have different doping concentrations. The semiconductor region, liner region, and trench region each have specifically controlled doping levels, allowing high current handling in the channel region while maintaining precise voltage threshold control through the lightly-doped liner and trench gate electrode regions.
Solution Approach 2:
The invention utilizes parameter changes in doping levels across different regions to simultaneously achieve high conductivity and voltage threshold control. By varying the doping concentration from the semiconductor region through the liner to the trench region, the device optimizes both current handling capability and voltage threshold characteristics without compromising manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the voltage threshold control and conductivity modulation, enabling the MOS transistor structures to effectively handle high current applications and provide robust ESD clamping, improving the overall performance and reliability of the transistors.
Implementation Method 1
A gate bias can be applied to the trench region and induce an electrostatic field in a silicon bulk layer immediately adjacent to the liner sidewall and modulate the conductivity of the silicon bulk
Implementation Method 2
the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure
Data Source
AI summary
A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.